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Power management
The power management system is highly flexible with functional blocks such as the CPU, Radio
Transceiver, and peripherals having separate power state control in addition to the global System
ON and OFF modes. In System OFF mode, RAM can be retained and the device state can be
changed to System ON through Reset,GPIO DETECT signal, or LPCOMP ANADETECT signal.
When in System ON mode, all functional blocks will independently be in IDLE or RUN mode
depending on needed functionality.
Power management features:
• Supervisor HW to manage
• Power on reset
• Brownout reset
• Power fail comparator
• System ON/OFF modes
• Pin wake-up from System OFF
• Reset
• GPIO DETECT signal
• LPCOMP ANADETECT signal
• Functional block RUN/IDLE modes
• RAM retention in System OFF mode (8 kB blocks)
• 16 kB version will have 2 blocks
• 32 kB version will have 4 blocks
System OFF mode
In system OFF mode the chip is in the deepest power saving mode. The system's core functionality
is powered down and all ongoing tasks are terminated. The only functionality that can be set up to
be responsive is the Pin wake-up mechanism.
One or more blocks of RAM can be retained while in System OFF mode.
System ON mode
In system ON mode the system is fully operational and the CPU and selected peripherals can be
brought into a state where they are functional and more or less responsive depending on the sub-
power mode selected.
There are two sub-power modes:
• Low power
• Constant latency
Low Power
In Low Power mode the automatic power management system is optimized to save power. This is
done by keeping as much as possible of the system powered down. The cost of this is that you will
have varying CPU wakeup latency and PPI task response.
The CPU wakeup latency will be affected by the startup time of the 1V7 regulator. The PPI task
response will vary depending on the resources required by the peripheral where the task originated.
The resources that could be involved are:
• 1V7 with the startup time
t
1V7
