System Considerations
CP381
Page 5 - 4
© 2002 PEP Modular Computers GmbH
ID 24107, Rev. 01
5.4
Debouncing
On the CP381 it is possible to select from a number of debouncing times, dependant on the
type of switches/sensors in use. For example, when using mechanical switches or relays to
switch the input, bouncing will always occur and therefore debouncing is necessary. A de-
bounce period may be selected from a range of values available, accessible via software in the
register depending on the settle time. Where it is known that an application does not generate
bouncing problems, the debounce period may be set to the default value.
5.5
Process-side Signal Conditioning
Considerations:
1. Input signals presented to the CP381 must be within the ranges specified for signals in
chapter 1.3.1 or erroneous results will occur as well as possible damage to the CP381.
5.6
Cable Interfacing
Considerations:
1. No modification to the CP381 itself is permitted.
2. If necessary, cabling to the CP381 CON2 connector should be physically fixed to prevent
strain on the CON2 connector.
Table 5-1: Debouncing Periods
Clock Divider
Input Sample Clock
@ 33 MHz PCI CLK
Input Sample Period
@ 33 MHz PCI CLK
1 (default value - see note below)
33 MHz
30 ns
2^8
128 kHz
8 us
2^10
32 kHz
32 us
2^12
8 kHz
128 us
2^14
2 kHz
0.5 ms
2^16
0.5 kHz
2 ms
2^18
125 Hz
8 ms
2^20
31 Hz
32 ms
*Note...
The clock divider default value is 1. In addition to the choice of debouncing fil-
ters, there is an analog filter implemented on board with an edge frequency at
10 kHz.
