PEP Modular Computers PMC251, Manual

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PMC251 Introduction
ID 19942, Rev. 0100 Page 1 - 8 ® PEP Modular Computers GmbH
1.5 Board Interfaces
1.5.1 PCI Bus Interface Block
The PMC251 is interfaced to the PCI bus via the TUNDRA PCI-to-local processor
bridge (QSPAN chip).
• 32-bit PCI interface capabilities on both the local bus (QBus) and the PCI Bus
• Master and slave capability on both busses
• Decoupled transfer technology: FIFO
• Four user programmable images
• Serial EEPROM interface for Plug and Play compatibility
• Interrupt generator on PCI and processor bus
• QSPAN control and status register accessible both from PCI and processor bus
Figure 1-3: PCI-to-Local Bridge Functional Block Diagram
1.5.2 PCI-to-Local Interface Block
The QSPAN PCI interface is made up of a PCI Master Module and a PCI Target Mod-
ule. For transfers from QBus to the PCI Bus the QSPAN provides the QBus slave chan-
nel. A transfer from the QBus to the PCI bus is initiated by a dedicated chip select
signal (CSPCI) whereas two independent, progammable slave images access PCI
memory and I/O spaces. Data transfers from QBus to PCI Bus are either posted (64
byte FIFO for zero wait state bursting on the PCI bus) or delayed accesses.
For the transfers from PCI to the QBus the PCI target channel is used. Two programma-
ble target images can be mapped anywhere in memory or I/O space. The transfers from
PCI to QBus can also be posted or delayed whereas these transactions are always buff-
ered. Therefore, delayed single transfers are buffered in the single transfer buffer, and
PCI Master
Module
QBus Slave
Module
PCI Target
Module
QBus Master
Module
Q-FIFO
I-FIFO
QBus Slave Channel
IDMA Channel
Register
Channel
Interrupter
P-FIFO
PCI Target Channel
PCI Bus
QBus