SCHEMATIC DIAGRAM OF MAIN BOARD (1/2)
PCO1
NATURAL
FLICKER
AGC_L/H
VCXO
ALC/ELC
D[4]
D[5]
CH2
D[6]
CH1
D[7]
SUB
PWM[3]
D[8]
V4
D[9]
PCO1
D[10]
AFIRQ
D[11]
HCLR
SYNC
PBLK
V3
V2
V1
LPF1
VCXO
FVR
SOUT0
FVD
RESET
D[0]
D[1]
D[2]
D[3]
LLDET2
BLC
AGC_L/H
NATURAL
FLICKER
VD2
BLC
ALC/ELC
ALC_DC
CBLK
CP2
SYNC
VD2
BFP
BFP
CP2
I2CSDA
I2CSCL
E2P_WP
E2P_WP
AFIRQ
FVD
LLDET2
CS
SDAT
PHOTO_OUT
SCLK
MOB
OSCIN
PCO0
PWM[2]
LPOUT
CXIN
RESET3.3V
OSCCNT
CPUPORT1
I2CSDA
PWM[4]
EASY_D/N
PWM[0]
PWM[1]
PWM[0]
VREF1
PWM[1]
VREF2
CLIP_LEV_X
EASY_D/N
FM_FREQ_X
CLIP_LEV_X
VREF1
VREF2
CBLK
FWHD
COIN
CXIN
ALC_DC
PBLK
ALC_VREF
FWHD
CS
FVD
SUB
HCLR
V1
D[10]
V2
D[8]
V3
D[6]
V4
D[4]
D[2]
ADCLK
D[0]
D[1]
ALC_VREF
YSIG
CSIG
CSIG
YSIG
OSCCNT
LPF1
CPUPORT1
ADCLK
PCO0
SLD0
CH1
SLD0
CH2
D[3]
D[5]
D[7]
D[9]
D[11]
PHOTO_OUT
OSCIN
MOB
RESET3.3V
SDAT
SCK0
SCLK
SOUT0
SCK0
PWM[2]
FVR
PWM[3]
ALC_DC
PWM[4]
FM_FREQ_X
LPOUT
RESET
COIN
I2CSCL
C41
0.1
GND
R8
0
R58
10k
GND
R71
OPEN
5V
R7
0
R67
OPEN
R65
3.9k
GND
3.3V
L8
OPEN
SGND2
R85
OPEN
R68
0
R63
0
R56
OPEN
GND
R74
OPEN
GND
C34
0.1
–8V
R75
OPEN
R57
OPEN
R60
OPEN
C40
10
X2
1
VC
2
NC
3
GND
4
OUT
5
OE
6
VDD
2.5V
R72
1k
R64
1M
C27
OPEN
R73
OPEN
C28
10
GND
R6
0
R52
1.5k
X1
OPEN
1
VC
2
NC
3
GND
4
OUT
5
OE
6
VDD
5V
Q2
G
S
D
R76
OPEN
OPEN
R69
OPEN
R53
0
5V
SGND1
C30
0.1
R55
470
R79
OPEN
L2
OPEN
C43
OPEN
R61
0
L5
OPEN
1
2
34
6
7
8
GND
R51
10k
L1
OPEN
R54
OPEN
LPF_2.5V
L6
R80
OPEN
GND
GND
R70
OPEN
15V
IC4
1
A_OUTPUT
2
A–INPUT
3
A+INPUT
4
GND
5
B+INPUT
6
B–INPUT
7
B_OUTPUT
8
V+
C36
0.1
MGND
R62
0
L7
3.3V
GND
2.5V
LPF_2.5V
R66
OPEN
5V
R77
100
3.3V
CN1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Attachment1
Attachment2
NATURAL
EASY_D/N
AGC_L/H
FLICKER
R91
2.2k
Q3
GND
3.3V
D4
OPEN
Q1
OPEN
G
S
D
C11
0.1
D2.5V
C1
0.1
IC1
1
TGVDD1
2
ADCLK
3
V1
4
V2
5
V3
6
V4
7
SUB
8
CH1
9
CH2
10
TGVSS1
11
R
12
H1
13
H1D
14
H2
15
H2D
16
TGVDD2
17
DS1
18
DS2
19
TGVSS2
20
DVSS1
21
DVDD1
22
FWHD
23
FVD
24
PBLK
25
CPOB
26
HCLR
27
DVSS2
28
DVDD2
29
ADIN11
30
ADIN10
31
ADIN9
32
ADIN8
33
ADIN7
34
ADIN6
35
ADIN5
36
ADIN4
37
ADIN3
38
ADIN2
39
ADIN1
40
ADIN0
41
EXTIN0
42
EXTIN1
43
EXTMODE
44
CHRIN
45
WCHRIN
46
TESTCLK
47
DVDD3
48
DVSS3
49
SIN1
50
SDIN
51
DSEP
52
SDOUT
53
DVSS4
54
DVDD4
55
SCK0
56
SOUT0
57
SCK1
58
SOUT1
59
CP2
60
BFP
61
DVSS5
62
DVDD5
63
FVR
64
VCXO
65
LPF1
66
DAVDD1
67
CSIG
68
DAVSS1
69
VREF2
70
VRO2
71
DAVDD2
72
YSIG
73
DAVSS2
74
VREF1
75
VRO1
76
AFIRQ
77
PCO1
78
PCO0
79
DVDD6
80
DVSS6
81
ROMDT0
82
ROMDT1
83
ROMDT2
84
ROMDT3
85
ROMDT4
86
ROMDT5
87
ROMDT6
88
ROMDT7
89
DVSS7
90
DVDD7
91
I2CSCL
92
I2CSDA
93
CPUPORT0
94
CPUPORT1
95
MRESETO
96
MRESETI
97
TEST0
98
TEST1
99
REVIRQ
100
TCK
101
XSM
102
XTST
103
SMCK
104
MST
105
DVDD8
106
DVSS8
107
BSIN
108
BDBMX
109
BRSTX
110
BEXCK
111
BSOUT
112
ROMADR0
113
ROMADR1
114
ROMADR2
115
ROMADR3
116
ROMADR4
117
ROMADR5
118
ROMADR6
119
ROMADR7
120
ROMADR8
121
ROMADR9
122
ROMADR10
123
ROMADR11
124
DVDD9
125
DVSS9
126
ROMADR12
127
ROMADR13
128
ROMADR14
129
ROMCSX
130
ROMRDX
131
ROMWRX
132
DVSS10
133
DVDD10
134
RESET
135
NTPAL
136
TEST2
137
TEST3
138
TEST4
139
ROMSEL0
140
ROMSEL1
141
MCKSEL
142
OSCSEL
143
OSCWAIT
144
DVSS11
145
CXOUT
146
CXIN
147
MD
148
DVDD11
149
CVD
150
CHD
151
CSYNC
152
CBLK
153
PCLKHALF
154
PWM0
155
PWM1
156
PWM2
157
PWM3
158
PWM4
159
PCLK
160
DVSS12
161
DVDD12
162
COIN
163
OSCCNT
164
GPIO0
165
GPIO1
166
GPIO2
167
GPIO3
168
GPIO4
169
GPIO5
170
GPIO6
171
GPIO7
172
GPIO8
173
GPIO9
174
GPIO10
175
GPIO11
176
GPIO12
C12
0.1
C2
0.1
C13
0.1
C21
0.1
C19
0.1
C15
0.1
C14
0.1
C3
0.1
GND
A2.5V
C20
0.1
C10
0.1
C17
0.1
C5
0.1
C6
0.1
C9
0.1
Q4
R14
1k
IC3
1
NC
2
IN_A
3
GND
4
OUT_Y
5
VCC
D2.5V
GND
C23
0.1
D2.5V
C38
OPEN
R20
11k
GND
C22
1
C24
OPEN
BLC
ALC/ELC
FM_FREQ_X
SYNC
CBLK
ALC_DC
CLIP_LEV_X
CP2
BFP
VD2
I2CSDA
I2CSCL
LLDET2
E2P_WP
AFIRQ
FVD
C26
OPEN
C29
1
C31
0.1
C37
OPEN
C39
OPEN
CS
SDAT
SCLK
PHOTO_OUT
OSCIN
MOB
LPOUT
RESET3.3V
CPUPORT1
GND
R36
0
R13
OPEN
D2.5V
R12
0
R37
100k
GND
R38
0
C18
1
GND
R41
10k
R39
OPEN
D3
OPEN
D2.5V
R11
10
R46
0
R19
0
R48
OPEN
R47
10
TD1
TD16
TD18
TD3
TD22
TD10
TD4
TD2
TD8
TD24
TD14
TD20
TD12
TD6
TD26
TD11
TD38
TD23
TD25
TD40
TD21
TD33
TD31
TD37
TD15
TD5
TD27
TD29
TD41
TD13
TD9
TD17
TD39
TD35
TD19
TD7
TD30
TD32 TD36
TD28
TD34
TD68
ALC_VREF
CSIG
YSIG
IC5
1
NC
2
IN_A
3
GND
4
OUT_Y
5
VCC
R84
OPEN
IC6
OPEN
1
IN_B
2
IN_A
3
GND
4
OUT_Y
5
VCC
R83
10k
TD72
TD73
TD74
TD75
TD76
R40
OPEN
R18
OPEN
R10
0
R9
OPEN
TD70 TD71
PCLK PCLK
IC2
1
VOUT
2
VSS
3
VIN
C54
0.1
2.5V
L9
C52
0.1
A2.5V
D2.5V
L10
GND
2.5V
GND
C53
10
GND
C55
10
GND
R35
0
R31
OPEN
R93
10k
R86
10k
D2.5V
GND
R100
10k
R99
10k
D2.5V
R94
10k
C4
10
R170
100k
GND
3.3V
R169
10k
Q8
GND
R22
10k
C35
1
GND
GND
C33
OPEN
C32
OPEN
C16
10
R16
2.7k
R17
2.7k
R173
130
R15
100
R92
240
R176
0
R177
OPEN
IC12
1
VOUT
2
VSS
3
VIN
3.3V
Q9
GND
V4
FWHD
D[9]
(NTSC)
2.5V
D[5]
CS
(56.75MHz)
ADCLK
GND
SCK0
15V
HCLR
OSCIN
SUB
GND
D[6]
3.3V
GND
(PAL)
D[2]
D[1]
MGND
GND
ALC_VREF
SDAT
V3
5V
SLDO
GND
PBLK
ALC_DC
GND
PHOTO_OUT
SCLK
D[7]
FVD
D[4]
CH1
–8V
D[8]
MOB
D[3]
SOUT0
GND
CH2
D[11]
RESET3.3V
V2
V1
D[0]
GND
D[10]
TO (2/2)
SCP-DSP
DSP RESET
LPF (VD2)
VCXO
PWM LPF
TO
SENSOR
BOARD
CN2
TD70,71
(14MHz)
DSP
<INDEX>
MAIN BOARD (1/2)
IC1 B3,B4,
C3,C4,
D3,D4
IC2 A4,A5
IC3 C7
IC4 C6
IC5 OPEN
IC6 OPEN
IC12 A5
Q1 OPEN
Q2 D6
Q3 A4
Q4 A3
Q8 A7
Q9 E3
D3 OPEN
D4 OPEN
MAIN BOARD (1/2)
1
A
B
C
D
E
2
3
4
5
6
7
4-2
