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14.20. DN-Board (3 of 3) Block Diagram
P3V_SCL2
P3V_SD
A2
P3V_SCL2
P3V_SDA2
P5V_DC
+1.2V
STB+1.5V
+3.3V
Q4718
+3.3V
STB+3.3V
+2.5V
+1.2V
Q4717
STB+5V
+3.3V
P5V_DC1
P5V_DC2
P+15V
+1.8V
5
+1.5V
62
FPGA_DCLK
OUT1
4
DN
51
21
VSYNC
S1
IIC_BUS
Q4306
CLK_O
24
OUT2
IC4001
15V->1.8V
LX
12
TC+
20
20
PO_A
CT
CB
PO_GE0-9
OUT2
50
9
13
PO_FLD
ROUT
P_ON/OFF
G1
VDD
18
-INC
BOUT
6
D5
-INC
5
13
TA-
PO_BE0-9
-INC
S1
10
CTL
PO_RE0-9
PO_GO0-9
D2
52
24
VSOE
7
OUT2
33
15V->2.5V
30
OSD_DATA0-15
CLKOE
S2
FPGA_DATA0
40
FHQCKIN
FPGA_NSTATUS
S2
IC4303
19
LX
VCOIN
23
27
24
G1
D2
E-LVDSCLK
+2.5V
23
18
GC_YO0-9
4
IC4309
VIN
TB+
GC_CO0-9
LX
25
44
6
E+LVDS1
55
15
FPGA_CONFDONE
D2
10bit LVDS
GC_VD
9
59
GC_HD
STB+3.3V
D1
44
CTL
O+LVDSCLK
1
20
57
ROE0-9
IC4301
64
G1
VIN
E+LVDSCLK
FHQCIN0-9
E+LVDS3
GC_CLK
5
TC+
D1
VIN
E-LVDS2
S1
FHQHIN
54
54
5
FHQVIN
TCLK+
E-LVDS0
48
O-LVDSCLK
5
1
TE-
TC-
O-LVDS1
28
IC4305
VDD
30
VIN
22
5
/PDWN
TA+
VDD
TC5
GC_GIN0-9
55
VOUT
D1
52
GC_RIN0-9
21
VDD
+3.3V
TCLK+
4
+1.8V
D2
E+LVDS2
VO
IIC_BUS
TC-
9
12
GC_BIN0-9
22
CB
18
21
GC_CLKIN
24
TD-
13
D1
1
VO
5
E-LVDS3
Q4301
46
33
14
CB
9
29
TA+
GC_HSIN
21
LX
6
OSD_HDO
GC_VSIN
9
BOUT
STB+1.5V
OSD_VDO
TE+
40
17
CTL
ROUT
31
5
O-LVDS3
VIN
8
CLKIN
O+LVDS1
IC4308
G2
17
11
-INC
IC5801
VOUT
23
24
1
29
PO_BO0-9
21
12
OSD_YS
PO_R
O0-9
VOUT
TD+
11
OSD_YM
(GC3E & HQ1)
TC4
D1
1
OSD_CLK
4
PORT-E
OSD-HD
19
10bit LVDS
5
OUT1
62
16
VCC
FB
TB-
TD-
38
5
30
OUT1
IC5301
20
18
15V->3.3V
VDD
TA-
28
/PDWN
TC5
CTL
G2
19
48
18
17
S2
20
46
O+LVDS4
24
TCLK-
D1
O-LVDS4
OUT2
E-LVDS1
VDD
E+LVDS4
23
64
42
D2
IC4304
P+15V
P+1.2V
59
16
VCC
19
23
24
13
TE+
20
TE-
9
FB
L
VDS-PD
TD+
15V->1.5V
HSYNC
17
OUT1
21
2
GOUT
D2
CLK0
FB
23
38
PO_CLK
P+15V
31
31
50
VO
8
TCLK-
25
63
CLK3
NRST
E+LVDS0
E-LVDS4
20
CLK7425
GOUT
TB-
P+15V
NRST
-FP
63
HSYNC
SD
A
1
G1
CLKIN
G2
SCL
19
18
61
G2
61
PO_VS
17
18
PO_HS
IC5802
23
CLK_O
S1
VSYNC
9
FPGA3
Q4302
CLKM_20MHz
CLK1
+1.5V
VOUT
CLK7425-1
IC4307
+2.5V
D1
13
29
25
VOUT
O+LVDS0
+3.3V
28
CB
O-LVDS0
42
19
FB
IC4004
TB+
Q4303
O-LVDS2
16
P+15V
25
NRST
O+LVDS3
16
GOE0-9
26
VO
S2
D2
VIN
21
VCC
IC4306
8
VCC
BOE0-9
11
O+LVDS2
P+5V
57
D1
HSOE
FPGA_NCONFIG
TC4
13
21
5
23
1
P+5V
D2
FPGA_DCLK
FHQYIN0-9
VDD
DIGITAL SIGNAL PROCESSOR
DN
STB 3.3V
STB 1.5V
1.2V REG
RGB 30bit OUT
GC5 PROCESOR
PORT-FHQ
[EVEN]
I-CHIPS RGB IN
GC_RGB IN
[ODD]
GC_YC OUT
OSD IN
LVDS OUT[ODD]
LVDS OUT[EVEN]
CONFIGURATION
DC-DC CONVERTER
DC-DC CONVERTER
DC-DC CONVERTER
AVR 5V
DC-DC CONVERTER
AVR 5V
TTL
P
ARALLEL
(SERIAL)
(SERIAL)
P
ARALLEL
[EVEN]
L
VDS
L
VDS
LVDS
TRANSMITTER
(10bit)
LVDS
TRANSMITTER
(10bit)
D
ATA
D
ATA
TTL
TH-50PF9UK
DN-Board (3 of 3) Block Diagram
TH-50PF9UK
DN-Board (3 of 3) Block Diagram
TH-50PF9UK
92
Summary of Contents for TH50PF9UK - 50" Plasma Panel
Page 4: ...1 Applicable signals 4 TH 50PF9UK ...
Page 19: ...7 Location of Lead Wiring 19 TH 50PF9UK ...
Page 20: ...20 TH 50PF9UK ...
Page 21: ...21 TH 50PF9UK ...
Page 24: ...8 4 Adjustment Volume Location 8 5 Test Point Location 24 TH 50PF9UK ...
Page 29: ...9 2 IIC mode structure following items value is sample data 29 TH 50PF9UK ...
Page 31: ...31 TH 50PF9UK ...
Page 33: ...33 TH 50PF9UK ...
Page 39: ...12 Option Setting 39 TH 50PF9UK ...
Page 72: ...TH 50PF9UK 72 ...
Page 73: ...14 Block and Schematic Diagram 14 1 Schematic Diagram Note TH 50PF9UK 73 ...
Page 139: ...15 Parts Location 15 1 Exploded View 15 1 1 The main mechanical parts relation 139 TH 50PF9UK ...
Page 141: ...15 3 Cable relation 141 TH 50PF9UK ...
Page 142: ...15 4 Packing summary 142 TH 50PF9UK ...
Page 143: ...143 TH 50PF9UK ...
Page 144: ...144 TH 50PF9UK ...
Page 145: ...145 TH 50PF9UK ...
Page 147: ...17 Replacement Parts List 17 1 Replacement Parts List Notes 147 TH 50PF9UK ...