Panasonic SDR-S45EG, Service Manual

Page: 61 / 105

S-48
INITIAL/LOGO ABBREVIATIONS
CHR BACK Character Back-up
CHR MIX Character Mix
CI, CO Buffer In/Out
CIF Control Signal Forward Input
CIF, CIR Positive Control Pulse, Negative Control Pulse
CIR Control Signal Reverse Input
CK Clock
CKSL System Clock Select
CL Clock
CLK Clock
CLASS Classeffication Signal for Compress (DCT/VLC)
CLASS 0.1 Class Control Signal Durring DCT/VLC
CLK135 13.5MHz System Clock
CLK27 27MHz System Clock
CLK450 450KHz Clock
CLKDCLK Digital Clock
CLK-PH Clock Phase Control
CLK-REF Reference Clock
CLP-RST-H Clamp Reset High Signal
CLV Constant Linear Velocity
CLX TFT X-axis Transmission Clock
CLX Shift Clock for X Direction (LCD Panel)
CLY Shift Clock for Y Direction (LCD Panel)
CLY TFT Y-axis Transmission Clock
CMEMO0-3 Chroma Memory Output Signal
CMIX Character Mix
CMO Chrominance Memory Output
CMODE Camera Mode
CNCLK Clock
CNR Chrominance Noise Reduction
CNT, CONT Control
CO Control Out
CO0-7 Chrominance Output (Digital)
COFTR Cap. OFF Track
COM Common
COM RDY Serial Enable Signal
COM RDY Serial Transmission Enable
COMB Comb Filter
COMPC Position Detection Pulse
COS EQ Cosin Equalizer
CP Clamp Pulse
CP ON Camera Power ON
CP2, 20 Clamp Pulse
CP2A, CP2O Encoder Clamp Pulse
CPA CPU Address
CPCS CPU Chip Select