13.1. (A) DSP Circuit
SCHEMATIC DIAGRAM - 1
DSP CIRCUIT
SCCLK
DATA7
DATA6
DATA5
DATA4
VD2
DGND2
DATA3
DATA2
DATA1
DATA0
AUDATA2
DC
DD
RESET
AGND
VA
FILT1
FILT2
CLKSEL
CLKIN
CMPREQ
CS
SCDOUT
INTREQ
EXTMEM
SDA
TAN1
VD3
DGND3
SCLKN1
LRCLKN1
CMPOA
T
CMPCLK
SCDIN
EMOE
EMWR
XMT958
DGND1
VD1
MCLK
SCLK
LRCLK
AUDA
TA
0
AUDA
TA
1
: +B SIGNAL LINE
JK1302
JK1301
DIGITAL IN DVR
(OPTICAL 2)
DIGITAL IN TV
(OPTICAL 1)
RX2
DSP_OFF
+5VA
RX1
C1311
0.1
RX0
2
1
3
VCC
GND
OUTPUT
VCC
GND
OUTPUT
2
1
3
JK1303
L1301
RLQZ150M-0
7
8
9
10
11
12
13
14
15
18 19 20 21 22 23 24 25 26
31
32
33
34
35
36
37
38
39
42
43
44
1
2
3
4
5
6
16
30
27
41
17
29
28
40
IC1001
C2HBZZ000015
AC3/DTS IC
IC1004
C0JBAZ002160
LOGIC IC
CDINV
MCLK
SCLK
LRCLK
AU0
AU1
AU2
CS49
CCLKV
SDOUT
R1014 10K
R1011 10K
R1007 10K
R1006 10K
R1008 10K
R1009 10K
R1012 10K
R1013 10K
1
2
13
14
3
12
4
11
5
10
6
9
7
8
R1004 3.3K
R1005 3.3K
VCC
4G
4A
4Y
3G
3A
3Y
1G
1A
1Y
2G
2A
2Y
GND
IC1005
C0JBAZ002161
LOGIC IC
1
2
13
14
3
12
4
11
5
10
6
9
7
8
VCC
4G
4A
4Y
3G
3A
3Y
1G
1A
1Y
2G
2A
2Y
GND
R1015
4.7K
CDINV
CDIN
CCLKV
CCLK
RST49
INT49
+2.5V
SCLK
+5VD
C1016 100P
CDOUT49
OMCK
R1003
10K
LRCLK
8
7
2
1
6
3
5
4
VCC
1Y
3A
2Y
1A
3Y
2A
GND
X1001
H0J122200002
IC1003
C0JBAB000633
LOGIC INVERTER IC
Q1001
B1GDCFJN0001
SWITCH
C1006
0.1
L1002
G1C2R2K00008
Z1101
J0JKB0000020
L1102
G1C2R2K00008
C1102
0.1
: MAIN SIGNAL LINE
COAXIAL IN DVD
C1005
50V1
R1017
4.7K
C1013
0.1
C1020
0.1
C1009
470P
C1008
50V2.2
C1011
6.3V100
R1025
0
R1016
33K
C1010
0.01
C1012
0.1
R1010
10K
C1027
100P
R1028
33
L1001
G1C2R2K00008
L1004
G1C2R2K00008
C1007
0.1
C1004
50V1
R1002
3.3K
R1001
3.3K
C1003
6.3V100
C1002
0.1
C1001
50V1
C1024
6.3V100
Q1001
C1022
0.1
C1018
1000P
R1021
1K
C1019
1000P
R1022
1K
R1020
1K
R1019
1K
C1015
100P
R1029
1K
R1026
100K
C1021
0.1
L1003
G1C2R2K00008
C1026
0.1
R1027
100K
R1030
1K
R1018
33
C1017
100P
R1023
1M
R1024
1K
C1025
22P
C1023
22P
C1301
0.01
C1302
0.1
L1302
VLQ0855M1R0T
C1308
6.3V100
C1309
0.01
C1303
0.01
C1304
0.1
C1306
0.1
R1301
75
C1307
0.1
R1302
10
C1305
0.1
C1310 0.1
R1303
10
28
SA-HT17PP
