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Panasonic PAN1322-SPP, User Manual

The Panasonic PAN1322-SPP is a cutting-edge device designed for seamless wireless communication. With its compact size and advanced features, this product brings convenience and efficiency to your electronic projects. Enhance your user experience by downloading the free user manual from manualshive.com to explore all the functionalities this device has to offer.

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PAN1322-SPP

ENW89841A3KF

 User’s Manual

30

Revision 1.3, 2013-08-14

Hardware Description

Package Information

8.2.1

Pin Mark

Pin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to 

Figure 8

. 

Diameter of pin 1 mark on the shield is 0.40mm.

Pin 1 marking bottom side

PAN1322 01/01

ENW89841A3KF
1302401
FCC ID:T7VEBMU

F2

F3

F4

F5

F6

E1

E2

E3

E4

E5

E6

E7

E8

E9

D1

D2

D3

D4

D5

D6

D7

D8

C1

C2

C3

C4

C5

C6

C7

C8

B1

B2

B3

B4

B5

B6

B7

B8

B9

A2

A3

A4

A5

A6

A7

A8

A1

F9

F7

F1

F8

D9

C9

A9

Pin 1 marking top side

Figure 8

Top View and Bottom View

Summary of Contents for PAN1322-SPP

Page 1: ...st 2013 User s Manual Hardware Description Revision 1 3 ENW89841A3KF Bluetooth QD ID B021246 End Product Listing FCC ID T7VEBMU IC ID 216QEBMU PAN1322 SPP Intel s BlueMoonUniversal Platform Wireless Modules ...

Page 2: ...n technology delivery terms and conditions and prices please contact your nearest Panasonic Office in Germany or one of our Distributor or write an e mail to wireless eu panasonic com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Panasonic Office Panasonic Electronic Devices may only be used i...

Page 3: ... s Manual 3 Revision 1 3 2013 08 14 Hardware Description PAN1322 SPP ENW89841A3KF Trademark Information BlueMoon is a trademark of Intel Mobile Communications GmbH IPhone iPad iPad and Apple are trademarks of Apple Inc ENW89841A3KF Intel s BlueMoonTM Universal Platform Revision History 2013 08 14 Revision 1 3 Previous Version 1 2 Revision Subjects major changes since last revision Rev1 0 Rev1 1 Re...

Page 4: ...Interface 16 3 1 1 UART 16 3 1 1 1 Baud Rates 16 3 1 1 2 Detailed UART Behavior 17 3 1 1 3 UARTCTS Response Time 17 3 2 Low Power Control 17 4 General Device Capabilities 18 4 1 RF Test Application 18 4 2 Firmware ROM Patching 18 4 2 1 Patch Support 18 5 Ordering Information 18 6 Bluetooth Capabilities 19 6 1 Supported Features 19 6 2 PAN1322 SPP Bluetooth Features 19 6 2 1 Secure Simple Pairing 1...

Page 5: ... Declaration of Conformity 34 9 7 Bluetooth Qualified Design ID 36 9 8 Industry Canada Certification 36 9 9 Label Design of the Host Product 36 9 10 Regulatory Test House 36 10 Assembly Guidelines 37 10 1 General Description of the Module 37 10 2 Printed Circuit Board Design 37 10 3 Solder Paste Printing 39 10 4 Assembly 39 10 4 1 Component Placement 39 10 4 2 Pin Mark 39 10 4 3 Package 40 10 5 So...

Page 6: ...7 Figure 6 Package Marking 29 Figure 7 Production Package 29 Figure 8 Top View and Bottom View 30 Figure 9 Reference Design Schematics 31 Figure 10 Cutout Drawing 33 Figure 11 Equipment Label 34 Figure 12 Declaration of Conformity 35 Figure 13 Pad Layout on the Module top view 37 Figure 14 Cutout Drawing 38 Figure 15 Pin Marking 39 Figure 16 Tape on Reel 40 Figure 17 Eutectic Lead Solder Profile 4...

Page 7: ...solute Maximum Ratings 21 Table 6 Operating Conditions 21 Table 7 Internal1 1 5 V Supplied Pins 22 Table 8 Internal2 2 5 V Supplied Pins 22 Table 9 VDDUART Supplied Pins 22 Table 10 VDD1 Supplied Pins 23 Table 11 ONOFF PIN 23 Table 12 Pull up and Pull down Currents 24 Table 13 Max Load at the Different Supply Voltages 25 Table 14 BDR Transmitter Part 25 Table 15 BDR Receiver Part 26 Table 16 EDR T...

Page 8: ... with HW flow control Default UART baudrate 115200 bit s Module configuration reprogrammable for 9600 bit s up to 3 25 Mbit s UART baudrate JTAG for boundary scan in production test RF Class 2 device up to 4 dBm Receiver sensitivity typ 86 dBm Integrated antenna balun and ISM band filter Integrated LNA with excellent blocking and intermodulation performance Digital demodulation for optimum sensiti...

Page 9: ...2 TDI F3 P0 11 F4 LPMin P0 14 F5 UARTCTS F6 VDDUART F7 UARTTXD F8 UARTRTS F9 VSS F11 VSS F12 VSS E1 P0 12 SDA0 E2 P0 13 SCL0 E3 P1 3 TDO E4 LPMout P0 0 E5 P0 1 E6 UARTRXD E7 NC E8 VSS E9 VSS D1 P0 10 D2 P0 8 D3 P1 1 TCK D4 P0 3 D5 P0 2 D6 NC D7 VSS D8 VSS D9 NC C1 VREG C2 P0 9 C3 JTAG C4 TRST C5 VDD1 C6 NC C7 NC C8 VSS C9 VSS B1 P1 7 B2 P1 8 B3 P1 0 TMS B4 P1 4 RTCK B5 ONOFF B6 NC B7 NC B8 NC B9 P...

Page 10: ... O OD Internal2 Z Z Port 1 4 or JTAG interface B5 ONOFF I Connect to VDD1 and refer to chapter 12 item 3 B9 SLEEPX I O VDDUART PD H Sleep indication signal C2 P0 9 I O OD Internal2 Z Z Port 0 9 C3 JTAG I Internal2 PU PU Mode selection Port 1 0 JTAG 1 Port C4 TRST I Internal2 PD PD JTAG interface D1 P0 10 I O OD Internal2 Z Z Port 0 10 D2 P0 8 I O OD Internal2 PD PD Port 0 8 D3 P1 1 TCK I O OD Inte...

Page 11: ...OD VDDUART PU PU Port 0 6 or UART RTS flow control A4 A5 A6 VSUPPLY SI Power supply C1 VREG SO Regulated Power supply F6 VDDUART SI UART interface Power supply C5 VDD1 SI Power supply A1 A7 A9 A11 A12 C8 C9 D7 D8 E8 E9 F1 F9 F11 F12 VSS Ground B6 B7 B8 C6 C7 D6 D9 E7 NC No connection 1 Fixed pull up pull down if JTAG interface is selected not affected by any chip reset If JTAG interface is not sel...

Page 12: ...ardware Description General Device Overview Descriptions of acronyms used in the pin list Input Output Output with open drain capability Tristate Pull up Pull down Analog e g AI means analog input Supply e g SO means supply output Acronym Description I O OD Z PU PD A S ...

Page 13: ...aterial BOM and a small PCB size Figure 3 shows a typical application example Example_Application_PAN1311 vsd BT Baseband BT Stack RFCOMM API BT RF Oscillator HOST I2 C BALUN RESET Antenna Loaded from EEPROM SPP Serial Port Profile AT interface UART command Keys Leds EEPROM Voltage Regulator VSUPPLY GPIO Figure 3 System Architecture Example of a Bluetooth System using eUniStone ...

Page 14: ...quired Additionally the host could hardware reset PAN1322 SPP using the RESET pin Power is supplied to a single VSUPPLY input from which internal regulators can generate all required voltages The UART and the GPIO s interfaces have separate supply voltages so that they can comply with host signaling 1 6 SW Patch in EEPROM Bug fixes for the SW in ROM are downloaded from the EEPROM Panasonic may inc...

Page 15: ...em clock is generated Also the low power mode clock of 32 768 kHz is generated internally which means that no external clock is needed 2 3 Low Power Modes To minimize current consumption eUniStone automatically switches between different low power modes The major modes are described below 2 3 1 Low Power Mode In Low Power Mode LPM most parts of eUniStone are powered down This is done automatically...

Page 16: ... levels to fit any system requirements 3 1 1 1 Baud Rates The UART baud rate can be configured with the BD_DATA parameter UART_Baudrate The module is programmed for a default baudrate of 115200 baud Reprogramming of the EEPROM configuration is possible by AT commands at manufacturing time of the end product The baudrate written to EEPROM will be used each time PAN1322 SPP starts or HW or SW reset ...

Page 17: ...etely transmitted While UARTCTS is high no data will be transmitted phase 2 When UARTCTS goes low again data transmission will continue phase 3 The maximum flow off response time is 10 UART bits including start and stop bits As an example if the UART baud rate is 115200 Baud the maximum flow off response time is 10 x 1 115200 s 87 µs HCI_UARTCTS_Response_Time vsd UARTCTS UARTTXD b it0 b it1 b it2 ...

Page 18: ...esign in even after the PAN1322 has been soldered in the final product The well proven patch concept used in PAN1322 is described below 4 2 1 Patch Support PAN1322 SPP contains dedicated hardware that makes it possible to apply patches to the code and data in the firmware ROM The hardware is capable of replacing up to 32 blocks of 16 bytes each with new content This area can be filled with any com...

Page 19: ...uest a role change to accomodate with other Bluetooth links If that happens the module will send an event to the host Also if the PAN1322 SPP start as slave Device B the other device can change it s own role making PAN1322 SPP master The host controlling PAN1322 SPP will be notified with the same event 6 2 3 Sniff Mode The local host or the remote device can request sniff mode for the link During ...

Page 20: ...uetooth Capabilities 6 2 6 Encryption Pause and Resume Encryption Pause Resume is supported making it possible to change connection link key on an encrypted link pause the encryption and resume it with the new link key This is handled automatically by PAN1322 SPP to make the link more secure ...

Page 21: ...ty Maximum ratings are absolute ratings exceeding only one of these values may cause irreversible damage to the integrated circuit Maximum ratings are not operating conditions 7 2 Operating Conditions Values 40 85 C 2 9 1 At ambient temperatures above 65 C the maximum allowed power dissipation in the module is limited to 200 mW 4 11 V 1 35 3 6 V 1 35 3 6 V Table 5 Absolute Maximum Ratings Paramete...

Page 22: ...h voltage Output low voltage Output high voltage Continuous Load1 1 The totaled continuous load for all Internal1 supplied pins shall not exceed 2mA at the same time Pin Capacitance Magnitude Pin Leakage Table 8 Internal2 2 5 V Supplied Pins Parameter Symbol Unit Note Test Condition Min Typ Max Input low voltage Input high voltage Input high voltage Output low voltage Output low voltage Output hig...

Page 23: ...DD1 2 5 V 5 mA 10 pF 0 01 1 μA Input and output drivers disabled Values 0 7 V 1 7 VSUPPLY V 1 0 01 1 μA ONOFF 0 V 1 The totaled continuous load for all VDDUART supplied pins shall not exceed 35 mA at the same time Table 10 VDD1 Supplied Pins Parameter Symbol Unit Note Test Condition Min Typ Max Input low voltage Input high voltage Output low voltage Output low voltage Output high voltage Output hi...

Page 24: ...t 40 C with supply 3 63 V 22 130 350 23 150 380 μA 4 2 24 68 3 0 20 55 μA 1 1 6 0 17 0 75 5 0 14 μA 7 3 3 Protection Circuits All pins have an inverse protection diode against VSS P0 10 has an inverse diode against Internal2 P0 5 UARTRXD has an inverse diode against VDDUART All other pins have no diode against their supply Table 12 Pull up and Pull down Currents Pin Pull Up Current Pull Down Curre...

Page 25: ...n Min Typ Max Vsupply Table 14 BDR Transmitter Part Parameter Symbol Values Unit Note Test Condition Min Typ Max Output power high gain 0 5 2 5 4 5 dBm Default settings Output power highest gain 4 5 dBm Maximum settings Power control step size 4 6 8 dB Frequency range fL 2400 2401 3 MHz Frequency range fH 2480 7 2483 5 MHz 20 dB bandwidth 0 930 1 MHz 2nd adjacent channel power 40 20 dBm 3rd adjace...

Page 26: ...but according to BT specification 39 34 dBm Valid for all intermodulation tests 20 dBm Table 15 BDR Receiver Part Parameter Symbol Unit Note Test Condition Min Typ Max Sensitivity C I performance 4th adjacent channel C I performance 3rd adjacent channel 1st adj of image C I performance 2nd adjacent channel image C I performance 1st adjacent channel C I performance co channel C I performance 1st ad...

Page 27: ...K RMS DEVM DPSK Peak DEVM 8DPSK Peak DEVM DPSK 99 DEVM 8DPSK 99 DEVM Differential phase encoding 1st adjacent channel power 2nd adjacent channel power 3rd adjacent channel power Table 17 EDR Receiver Part Parameter Symbol Values Unit Note Test Condition Min Typ Max DQPSK Sensitivity 88 83 dBm Ideal wanted signal 8DPSK Sensitivityl 83 77 dBm Ideal wanted signal DQPSK BER Floor Sensitivity 84 60 dBm...

Page 28: ...performance 3rd adjacent channel 1st adj of image 44 13 dB 8DPSK C I performance 2nd adjacent channel image 25 0 dB 8DPSK C I performance 1st adjacent channel 5 5 dB 8DPSK C I performance co channel 17 21 dB 8DPSK C I performance 1st adjacent channel 5 5 dB 8DPSK C I performance 2nd adjacent channel 36 25 dB 8DPSK C I performance 3rd adjacent channel 46 33 dB Maximum input level 20 dBm Table 17 ED...

Page 29: ...8 PAN1322 ENW89841A3KF YYWWDLL FCC ID T7VEBMU Version HW Hardware Version SW Software Version Ordering Code Date Code FCC ID Machine readable 2D bar code Panasonic usage only could be changed without any notice Case PCB HW SW Figure 6 Package Marking 8 2 Production Package Figure 7 Production Package All dimensions are in mm Tolerances on all outer dimensions height width and length are 0 2 mm ...

Page 30: ... shield on the module according to Figure 8 Diameter of pin 1 mark on the shield is 0 40mm Pin 1 marking bottom side PAN1322 01 01 ENW89841A3KF 1302401 FCC ID T7VEBMU F2 F3 F4 F5 F6 E1 E2 E3 E4 E5 E6 E7 E8 E9 D1 D2 D3 D4 D5 D6 D7 D8 C1 C2 C3 C4 C5 C6 C7 C8 B1 B2 B3 B4 B5 B6 B7 B8 B9 A2 A3 A4 A5 A6 A7 A8 A1 F9 F7 F1 F8 D9 C9 A9 Pin 1 marking top side Figure 8 Top View and Bottom View ...

Page 31: ... 1 3 2013 08 14 Hardware Description PAN1322 SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification 9 Bluetooth Qualification and Regulatory Certification 9 1 Reference Design Figure 9 Reference Design Schematics ...

Page 32: ...provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause ...

Page 33: ...n 1 3 2013 08 14 Hardware Description PAN1322 SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification Figure 10 Cutout Drawing Manufacturers of mobile fixed or portable devices incorporating this module are advised to clarify any regulatory questions and to have their complete product tested and approved for FCC compliance 9 4 FCC Interference Statement This device complies with Part...

Page 34: ...841A3KF is in compliance with the essential requirements and other relevant provisions of Directive 1999 5 EC As a result of the conformity assessment procedure described in Annex III of the Directive 1999 5 EC the end customer equipment should be labelled as follows Figure 11 Equipment Label PAN1322 in the specified reference design can be used in the following countries Austria Belgium Cyprus Cz...

Page 35: ...User s Manual 35 Revision 1 3 2013 08 14 Hardware Description PAN1322 SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification Figure 12 Declaration of Conformity ...

Page 36: ...es incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and or RF exposure limits Users can obtain Canadian information on RF exposure and compliance from www ic gc ca This device has been designed to operate with the built in antenna It is not allowed to alter the antenna or connecting an external antenna to the module The built in antenna used f...

Page 37: ...ents and shield will stay in place due to wetting force Wave soldering is not possible Surface treatment on the module pads is Nickel 5 8 µm Gold 0 04 0 10 µm Figure 13 shows the pad layout on the module seen from the component side F2 F3 F4 F5 E1 E2 E3 E4 E5 E6 E7 E8 E9 D1 D2 D3 D4 D5 D6 D7 D8 C1 C2 C3 C4 C5 C6 C7 C8 B1 B2 B3 B4 B5 B6 B7 B8 B9 A2 A3 A4 A5 A6 A7 A8 A1 1 0 8 70 mm 0 6 5 0 0 6 1 35 ...

Page 38: ...r of main PCB PAN1322 SPP ENW89841A3KF User s Manual 38 Revision 1 3 2013 08 14 Hardware Description Assembly Guidelines Figure 14 Cutout Drawing In order to preserve the characteristics of the embedded antenna a cutout must be respected under the antenna through all metal layers of the PCB as shown in drawing Figure 14 Placing the module inside a metal housing or close to metal parts like fastene...

Page 39: ...ent is 150 µm This means that the PAN1322 module can be assembled with a variety of placement systems It is recommended to use a vision system capable of package pad recognition and alignment that evaluates the pad locations on the package in contrast to outline centring This eliminates the pad to package edge tolerance The recommendation is to pick and place the module with a nozzle in the centre...

Page 40: ... PAN1322 SPP ENW89841A3KF User s Manual 40 Revision 1 3 2013 08 14 Hardware Description Assembly Guidelines 10 4 3 Package PAN1322 is packed in tape on reel according to Figure 16 Figure 16 Tape on Reel ...

Page 41: ...gure 17 and Figure 18 shows example of a suitable solder reflow profile One for leaded and one for leadfree solder Lead _Solder _Profile vs d Recommended temp profile for reflow soldering Temp C Time s 235 C max 220 5 C 200 C 150 10 C 90 30s 10 1s 30 20 10s Figure 17 Eutectic Lead Solder Profile LeadF ree _Solder _Profile v sd 25 C 150 C 200 C 217 C 255 C 260 C 60 120 sec 3 C sec max 60 150 sec 30...

Page 42: ... s and max sloping rate should not exceed 4 C s PAN1322 shall be handled according to MSL3 which means a floor life of 168h in 30 C 60 r h The PAN1322 module can be soldered according to max J STD 020C curve assuming that all other conditions are followed stated in Product Specification Qualification Report and in Application Note Restriction is that PAN1322 can be soldered two times since one tim...

Page 43: ...tencil upside down 7 Separate carefully the bottom from the fixture 8 Pick the module by a nozzle and place in the right position on the board 9 Reflow the solder 10 7 Inspection Automatic inspection of the solder paste printing before assembly is highly recommended to ensure high yield and good long term reliability 10 8 Component Salvage If it is intended to send a defect PAN1322 module back to ...

Page 44: ...D 10 9 2 Parameters with an Impact on Voiding If the void content has to be reduced following parameters have an impact Solderability on module and PCB Bad solderability is often connected to oxidation and has therefore a major impact on voiding Flux will get entrapped on oxidized surfaces In general Ni Au pads show fewer voids than HASL and OSP Solder paste Higher activity of the flux will remove...

Page 45: ...ncil means more surface area to the air and thereby easier for the outgassing flux to leave the solder Temperature soldering profile Too short preheat time means that the flux does not get enough time to react and flux get entrapped in the solder and create voids Too long reflow time gives larger voids Too short reflow time gives a fraction of voids ...

Page 46: ...ooth BW Bandwidth C CMOS Complementary Metal Oxide Semiconductor COD Class Of Device CODEC COder DECoder CPU Central Processing Unit CQDDR Channel Quality Driven Data Rate CRC Cyclic Redundancy Check CTS Clear To Send UART flow control signal CVSD Continuous Variable Slope Delta modulation CDCT Clock Drift Compensation Task CQDDR Channel Quality Driven Data Rate D DC Direct Current DDC Device Data...

Page 47: ... modulation GPIO General Purpose Input Output GSM Global System for Mobile communication H HCI Host Controller Interface HCI Infineon Specific HCI command set HEC Header Error Check HV High quality Voice packet type HW Hardware I I2C Inter IC Control bus I2S Inter IC Sound bus IAC Inquiry Access Code ID IDentifier IEEE Institute of Electrical and Electronics Engineers IF Intermediate Frequency ISM...

Page 48: ...d Modulation PDU Protocol Data Unit PER Packet Error Rate PIN Personal Identification Number PLC Packet Loss Concealment PLL Phase Locked Loop PMU Power Management Unit POR Power On Reset PTA Packet Traffic Arbitration PTT Packet Type Table Q QoS Quality Of Service R RAM Random Access Memory RF Radio Frequency ROM Read Only Memory RSSI Received Signal Strength Indication RTS Request To Send UART f...

Page 49: ...Test Clock JTAG signal TDI Test Data In JTAG signal TDO Test Data Out JTAG signal TL Transport Layer TMS Test Mode Select JTAG signal TX Transmit TXD Transmit Data UART signal U UART Universal Asynchronous Receiver Transmitter ULPM Ultra Low Power Mode V VCO Voltage Controlled Oscillator W WLAN Wireless LAN Local Area Network ...

Page 50: ...eUniStone_1 00_SW_3 1_RN pdf Always the latest revision will be available under the link below please refer also to Table 2 Firmware Releases as of 2013 05 14 on Page 14 SPP AT Release Notes 3 PAN1322 Application Note Design Guide Always the latest revision as a pdf file will be available under the link below PAN1322 Application Note Design Guide 4 PAN1322 SPP User s Manual Data Sheet It is this d...

Page 51: ...User s Manual 51 Revision 1 3 2013 08 14 Hardware Description PAN1322 SPP ENW89841A3KF References ...

Page 52: ...Published by Panasonic Industrial Devices Europe GmbH w w w p i d e u p a n a s o n i c d e ...

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