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Closed-Caption Decoder

Closed-Caption Decoder Registers

MN102H75K/F75K/85K/F85K LSI User Manual

Panasonic Semiconductor Development Company

245

Panasonic

BSP[5:0]: Sync separator level for pedestal clamping

Sync separator level = (sync tip level/2) + BSP[5:0]. The valid range is
x’00’ to x’3F’.

PSP[5:0]: Sync separator level for sync tip clamping

Valid range: x’00’ to x’3F’

CLAMP: Clamping Control Register

x’007ECC’

(CLAMPW

x’007EEC’)

Use this register to set the clamping mode (sync tip or pedestal clamping).

PCLV[6:0]: Pedestal clamping level setting

Set the reference level for pedestal clamping in this field. The valid range
is x’00’ to x’7F’.

VBION: VBI setting

0: VBI off
1: VBI on

SAFE: Clamping current source select

This bit is the capacity switch for (5) and (6) in figure 9-5 on page 229.

0: High current source ((5) and (6) capacity high)
1: Medium current source ((5) and (6) capacity low)

CLMODE[1:0]: Clamping mode setting

00: Automatic switching (depends on the cycle state)

01: Sync tip clamping only
10: Pedestal clamping only

11: Clamping off

Figure 9-15 BSP and PSP Multiplexing

Bit:

—

PCLV6 PCLV5 PCLV4 PCLV3 PCLV2 PCLV1 PCLV0 SAFE

—

VBI

—

MODE

Reset:

R/W:

R/W

MUX

Compare

CLMODE

BSP

PSP

Composite signal

from ADC

Composite sync

Summary of Contents for MN10285K

Page 1: ...MICROCOMPUTER MN102H MN102H75K F75K 85K F85K LSI User s Manual Pub No 22385 011E ...

Page 2: ......

Page 3: ...f this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes 3 We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party 4 No part of this book may be repri...

Page 4: ...iption 31 1 7 Bus Interface 35 1 7 1 Description 35 1 7 2 Bus Interface Control Registers 36 2 Interrupts 37 2 1 Description 37 2 2 Interrupt Setup Examples 40 2 2 1 Setting Up an External Pin Interrupt 40 2 2 2 Setting Up a Watchdog Timer Interrupt 42 2 3 Interrupt Control Registers 44 3 Low Power Modes 72 3 1 CPU Modes 72 3 1 1 Description 72 3 1 2 Exiting from SLOW Mode to NORMAL Mode 73 3 1 3 ...

Page 5: ...Using Timer 5 117 4 11 9 Setting Up an External Count Direction Controller Using Timer 5 120 4 11 10 Setting Up External Reset Control Using Timer 5 123 4 12 16 Bit Timer Control Registers 125 5 Serial Interfaces 127 5 1 Description 127 5 2 Features 127 5 3 Connecting the Serial Interfaces 128 5 3 1 Synchronous Serial Mode Connections 128 5 3 2 UART Mode Connections 128 5 3 3 I2 C Mode Connection ...

Page 6: ...ls 156 7 5 3 Multi Layer Format 156 7 5 4 Output Pin Setup 157 7 5 5 Microcontroller Interface 157 7 5 6 VRAM 157 7 5 7 Conditions for VRAM Writes 158 7 6 Standard and Extended Display Modes 159 7 6 1 Cursor Layer Display Modes 159 7 6 2 Graphics Layer Display Modes 160 7 7 Display Setup Examples 161 7 7 1 Setting Up the Graphics Layer 161 7 7 2 Setting Up the Text Layer 163 7 8 VRAM 165 7 8 1 VRA...

Page 7: ... 5 1 Leader Detection 221 8 3 5 2 Trailer Detection 221 8 3 5 3 8 Bit Data Reception Detection 221 8 3 5 4 Pin Edge Detection 221 8 3 6 Controlling the SLOW Mode 222 8 4 IR Remote Signal Receiver Control Registers 223 9 Closed Caption Decoder 227 9 1 Description 227 9 2 Block Diagram 227 9 3 Functional Description 228 9 3 1 Analog to Digital Converter 228 9 3 2 Clamping Circuit 229 9 3 3 Sync Sepa...

Page 8: ...er Receiver 300 13 6 1 1 Pre configuring 300 13 6 1 2 Setting Up the First Interrupt 300 13 6 1 3 Setting Up the Second Interrupt 301 13 6 1 4 Setting Up the Third Interrupt 301 13 6 2 Setting Up a Transition from Slave Receiver to Slave Transmitter 302 13 6 2 1 Pre configuring 302 13 6 2 2 Setting Up the First Interrupt 302 13 6 2 3 Setting Up the Second Interrupt 303 13 6 2 4 Setting Up the Thir...

Page 9: ... Writer Interface Block Diagram 322 B 4 4 Microcontroller Memory Map Used During Onboard Serial Programming 323 B 4 4 1 Flash ROM Address Space 323 B 4 4 2 RAM Address Space 324 B 4 5 Microcontroller Clock on the Target Board 324 B 4 6 Setting Up the Onboard Serial Programming Mode 325 B 4 7 Branching to the User Program 327 B 4 7 1 Branching to the Reset Start Routine 327 B 4 7 2 Branching to the...

Page 10: ...129 5 3 Serial Interface Control Registers 140 6 1 ADC Functions and Features 143 6 2 ADC Control Registers 150 7 1 OSD Functions and Features 153 7 2 Power Saving Control Bits for the OSD 155 7 3 OSDPOFF and OSDREGE Settings 155 7 4 Associated Tiles for Cursor Tile Code Registers 160 7 5 Example Graphics VRAM Settings 161 7 6 Example Text VRAM Settings 163 7 7 VRAM Bit Allocation in Internal RAM ...

Page 11: ...Pins 251 12 1 ROM Correction Address Match and Data Registers 290 13 1 I2C Bus Terminology 293 13 2 Operating Modes for Devices on an I2 C Bus 294 13 3 Control Registers for Clamping Circuit 296 13 4 Registers Settings for SDA0 SCL0 or SDA1 SCL1 Ports 298 13 5 SDA and SCL Waveform Characteristics 299 13 6 STA and STO Settings 304 14 1 H Counter Pins 308 A 1 Register Map x 007E00 to x 007FFF 312 A ...

Page 12: ... Diagram of External Pin Interrupt 40 2 5 Timing for External Pin Interrupt Setup Example 41 2 6 Block Diagram of Watchdog Timer Interrupt 42 2 7 Timing for Watchdog Timer Interrupt Setup Example 43 3 1 CPU State Changes 72 3 2 CPU Clock Switch NORMAL SLOW Modes 73 4 1 Timer Configuration Examples 77 4 2 Block Diagram of 8 Bit Timers 77 4 3 Timer 0 Block Diagram 79 4 4 Timer 1 Block Diagram 79 4 5...

Page 13: ...re Input Using Timer 5 111 4 40 Configuration Example 1 of 4x Two Phase Capture Input Using Timer 5 111 4 41 Configuration Example 2 of 4x Two Phase Capture Input Using Timer 5 111 4 42 4x Two Phase Encoder Input Timing Timer 5 113 4 43 Block Diagram of 1x Two Phase Capture Input Using Timer 5 114 4 44 Configuration Example 1 of 1x Two Phase Capture Input Using Timer 5 114 4 45 Configuration Examp...

Page 14: ...ation When GEXTE 0 169 7 7 Graphics VRAM Organization for Two Modes 170 7 8 Timing for OSD data 171 7 9 ROM Organization 172 7 10 Graphics ROM Setup Example for a Single Line 173 7 11 Graphics ROM in the Four Color Modes 16W x 16H Tiles 174 7 12 Graphics ROM in the Four Color Modes 16W x 18H Tiles 175 7 13 Graphics ROM Organization in 16 Color Mode 16W x 16H Tiles 176 7 14 Graphics ROM Organizatio...

Page 15: ...ircuit Block Diagram 231 9 7 HSYNC Securement and Interpolation 232 9 8 VSYNC Masking 233 9 9 Data Slice Level Calculation 233 9 10 Sampling Clock Timing Determination 235 9 11 Caption Data Capture Timing 235 9 12 SLSF and SLHD Multiplexing 238 9 13 Backporch Position Setting 244 9 14 Sync Separator Level 244 9 15 BSP and PSP Multiplexing 245 10 1 PWM Output Waveform 249 10 2 PWM Block Diagram 250...

Page 16: ...95 13 4 I2 C Bus Controller Block Diagram 296 13 5 Pin Control Circuit for the I2 C Bus Controller 298 13 6 SDA and SCL Waveforms 299 13 7 Waveform for Master Transmitter Transitioning to Master Receiver 301 13 8 Waveform for Slave Receiver Transitioning to Slave Transmitter 303 14 1 H Counter Block Diagram 307 14 2 H Counter Operation Example 307 14 3 H Counter Input Signal Timing 308 B 1 Memory ...

Page 17: ...ix A provides a register map and Appendix B describes the flash EEPROM version Text Conventions Where applicable this manual provides special notes and warnings Helpful or supplementary comments appear in the sidebar In addition the following symbols indicate key information and warnings Register Conventions This manual presents 8 and 16 bit registers in the following format REGISTER Register Name...

Page 18: ...he C compiler MN102H Series C Compiler User Manual Language Description Describes the syntax for the C compiler MN102H Series C Compiler User Manual Library Reference Describes the standard libraries for the C compiler MN102H Series Cross Assembler User Manual Describes the assembler syntax and notation MN102H Series C Source Code Debugger User Manual Describes the use of the C source code debugge...

Page 19: ...w system power consumption The devices in this series contain up to 16 megabytes of linear address space and enable highly efficient program development In addition the optimized hardware structure allows for low system wide power consumption even in large systems 1 2 MN102H Series Features Designed for embedded applications the MN102H series contains a flexible and optimized hardware architecture...

Page 20: ... With this architecture the MN102H series can execute single byte instructions in only one machine cycle 50 ns at 40 MHz Simple instruction set The MN102H series uses a streamlined set of 41 instructions designed spe cifically for the programming model for embedded applications To shrink code size instructions have a variable length of one to seven bytes and the most frequently used basic instruct...

Page 21: ...h class can be set to one of seven priority levels This gives the software designer great flexibility and fine control The core is also backwards compatible with software from previous Panasonic peripheral modules High speed high functionality external interface The MN102H series provides DMA handshaking bus arbitration and other functions that ensure a fast efficient interface with other devices ...

Page 22: ... results ST Saturation This bit controls whether or not the CPU calculates a saturation limit for an operation When it is set to 1 the CPU executes a saturate operation and when it is 0 the CPU executes a normal operation The PXST instruction can reverse the meaning of this bit for the next and only the next instruc tion S 1 0 Software control These bits are the control field for OS software It is...

Page 23: ...ag is set oth erwise it is reset VF Overflow flag If the operation causes the sign bit to change in a 16 bit signed number this flag is set otherwise it is reset CF Carry flag If the operation resulted in a carry into from addition or a borrow out of from subtraction or a comparison bit 15 this flag is set otherwise it is reset NF Negative flag If bit 15 of the result of an operation has the value...

Page 24: ...ruction being executed The four address registers specify the location of the data in the memory A3 is assigned as the stack pointer The four data registers handle all arithmetic and logic operations When byte length 8 bit or word length 16 bit data is to be transferred to memory or to another register an instruction adds a zero or sign extension The dedicated multiplication division register stor...

Page 25: ...the instructions and the font data for the on screen display OSD in any location The internal RAM contains the MCU data and the VRAM for the OSD in any location Figure 1 5 Address Space Special Function Registers Internal RAM Internal ROM Program OSD Text fonts Graphic tiles Data OSD Text VRAM Graphics VRAM Special Function Registers x 007E00 x 007FFF x 008000 x 009FFF x 00FC00 x 00FFFF x 080000 x...

Page 26: ...ontrol hardware configuration varies between products Figure 1 6 Interrupt Controller Configuration 0 1 2 3 4 5 6 Interrupt Masking Nonmaskable Interrupt Receive Reset Receive Interrupt Enable Maskable Interrupt Receive Reset CPU Core 4 Group 4 Maskable Interrupt Controllers Maskable Interrupt Control Registers xx ICR 4 External NMI pin input Watchdog timer Undefined instruction Interrupt occurred...

Page 27: ...gister Instruction set 41 instructions 6 addressing modes 1 byte basic instruction length Code assignment 1 byte basic 0 to 6 bytes extension Performance 12 MHz internal operating frequency with a 4 MHz external oscilla tor Instruction execution clock cycles Minimum 1 clock cycle 83 3 ns for register to register operations Minimum 1 clock cycle 83 3 ns for load store operations Minimum 2 clock cyc...

Page 28: ...ltimaster 2 channel with 1 internal circuit Analog to digital converter 8 bit with 12 channels Automatic scanning IR remote signal receiver Automatic HEAMA 5 6 bit detection 1 bit interrupt PWM 8 bit with 7 channels 3 3 volt tolerance Closed caption decoder 2 channels Internal sync separator On screen display Three layer format Text layer 16 18 pixels 16 26 in closed caption mode blink ing outlini...

Page 29: ...urce Instruction execution controller Instruction decoder Quick decoder Interrupt controller Instruction queue Peripherals extension bus Interrupt bus Internal peripheral functions BG BR External extension bus External interface RAM bus Internal RAM Internal ROM ROM bus B u s c o n t r o l l e r Operand address Program address Program Counter Incrementer ALU Address registers Data registers A B Mu...

Page 30: ... Arithmetic and logic unit This block calculates the operand addresses for arithmetic operations logic operations shift opera tions relative indirect register addressing indexed addressing and indirect register addressing Multiplier This block multiplies 16 bits 16 bits 32 bits Internal ROM and RAM These memory blocks contain the program data and stack areas Address registers An The address regist...

Page 31: ...46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS OSC2 OSC1 VDD P61 SCL0 P60 SDA0 P57 SBT0 P56 SBI0 SBD0 P55 SBO0 P54 IRQ5 VSYNC P53 RST P52 IRQ4 VI0 TEST P51 YS P50 SYSCLK P47 HSYNC P46 OSDXI P45 OSDXO P44 TM5IC HI1 P43 TM5IOB HI0 P42 TM5IOA P41 TM1IO VCOI PDO P40 DAYMOUT YM P37 DABOUT B P36 DAGOUT G P35 DAROUT R VREF P34 IREF COMP AVDD P00 RMIN IRQ0 P01 SDA1 P02 SCL1 P03 ADIN0 P04 ADIN1 P05 ADIN2 P0...

Page 32: ...8 77 76 75 74 73 72 71 70 69 68 67 66 65 64 NC P71 P10 ADIN5 IRQ1 P11 ADIN6 IRQ2 P12 ADIN7 IRQ3 P72 P13 ADIN8 WDOUT P14 ADIN9 STOP P73 P15 ADIN10 PWM0 P16 ADIN11 PWM1 P17 PWM2 P20 PWM3 P21 PWM4 P22 PWM5 P23 PWM6 P24 TM4IC SBT1 P25 TM4IOB SBI1 SBD1 P26 TM4IOA SBO1 P27 TM0IO P74 P85 NC P56 SBI0 SBD0 P57 SBT0 P60 SDA0 P86 P61 SCL0 VDD OSC1 OSC2 VSS P87 P00 RMIN IRQ0 P01 SDA1 P02 SCL1 P03 ADIN0 P04 AD...

Page 33: ... P45 Reset RST I O 1 Reset alt function P53 Interrupts external IRQ0 IRQ5 I 6 External interrupt request to microcontroller alt functions P00 P10 P11 P12 P52 P54 OSD HSYNC I 1 Horizontal sync signal input VSYNC I 1 Vertical sync signal input YS O 1 Video signal cut Timers 16 bit 2 TMnIOA n 4 5 I O 2 Input capture output compare A TMnIOB n 4 5 I O 2 Input capture output compare B TMnIC n 4 5 I 2 Ti...

Page 34: ...vel high input CLL I 1 Clamp level low input VREFHS I 1 CCD reference voltage input VREFLS I 1 CCD reference voltage input A D converter 12 channel ADIN0 ADIN11 I 12 Analog signal input D A converter 4 bit 4 channel DAROUT 1 O 1 DAC output red DAGOUT 1 O 1 DAC output green DABOUT 1 O 1 DAC output blue DAYMOUT 1 O 1 DAC output YM IREF I 1 Resistance connection for DAC bias current setting VREF I 1 ...

Page 35: ...l and analog supplies connect the pins in the location closest to the power supply Figure 1 11 Power Supply Wiring Note The capacitance values vary depending on the oscillator Figure 1 12 OSC1 and OSC2 Connection Examples Figure 1 13 Reset Pin Connection Example 1 Note The capacitance values vary depending on the oscillator Figure 1 14 OSDXI and OSDXO Connection Examples Power Supply VDD VSS VDD V...

Page 36: ...ternal RAM 8192 bytes 3 Peripheral registers External devices Internal masked ROM 256 Kbytes 1 External devices Expandable up to 16 MB Reset start External Expansion Mode x FFFFFF x 200000 x 400000 x 800000 x C00000 x 0C0000 2 x 080000 x 010000 x 00FC00 x 00A000 4 x 008000 x 000000 External memory space 0 CS0 signal MN102H75K 1 256 Kbytes 2 x 0C0000 3 8192 bytes 4 x 00A000 External memory space 1 ...

Page 37: ...rite 0s to bits 15 to 2 IOW 1 0 Wait setting for internal I O space 00 1 wait 01 Reserved 10 2 waits 11 3 waits Bi t 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EW 33 EW 32 EW 31 EW 30 EW 23 EW 22 EW 21 EW 20 EW 13 EW 12 EW 11 EW 10 EW 03 EW 02 EW 01 EW 00 Reset 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Table 1 4 Wait Count Settings EW n3 n0 Sett...

Page 38: ...nd external pins must be registered in an interrupt group controller Once they are registered interrupt requests are sent to the CPU in accordance with the interrupt mask level 0 to 6 set in the interrupt group controller Groups 1 to 3 are dedicated to system interrupts Table 2 1 compares the interrupt parameters of the MN102H75K 85K to those of the MN102L35G the com parable MCU in the previous ge...

Page 39: ...oup 18 Timer 4 underflow interrupt Group 19 VBI interrupt 1 Class 4 00FC62 R W 00FC64 R W 00FC66 R W 00FC60 R W Group 20 Timer 5 compare capture B Group 21 Timer 5 compare capture A Group 22 Timer 5 underflow interrupt Group 23 VBI interrupt 2 Class 5 00FC6A R W 00FC6C R W 00FC6E R W 00FC68 R W Group 24 Timer 2 underflow interrupt Group 25 Timer 1 underflow interrupt Group 26 Timer 0 underflow int...

Page 40: ...ss for interrupt service routine mov BASE A0 mov D0 A0 A0 3 2 1 2 Branch jsr A0 2 5 Total 17 15 Table 2 3 Handler Postprocessing Sequence Assembler Bytes Cycles Pop registers mov A3 A0 movx 4 A3 D0 add 8 A3 2 3 2 2 3 1 Total 7 6 Program Interrupt Max 6 cycles Interrupt hardware processing 9 cycles Handler preprocessing Interrupt service routine Handler postprocessing Address 80008 jsr 5 cycles rts...

Page 41: ...et the IQ0TG 1 0 bits of EXTMD to b 10 negative edge triggered interrupt EXTMD example x 00FCF8 2 Cancel any existing interrupt requests and enable IRQ0 interrupts To do this set the IQ0IR bit of IQ0ICL to 0 set the IQ0LV 2 0 bits of IQ0ICH to b 101 priority level 5 and set the IQ0IE bit to 1 IQ0ICL example x 00FC48 IQ0ICH example x 00FC49 Figure 2 4 Block Diagram of External Pin Interrupt IRQ0 P5...

Page 42: ...rupt group number register IAGR to determine the interrupt group group 4 in this case 5 Branch to the interrupt service routine During the interrupt service rou tine prevent the CPU from accepting any other maskable interrupts by setting the IM 2 0 and IE bits of the PSW to 0 6 At the beginning of the interrupt service routine clear the IQ0IR bit in IQ0ICL to 0 To accept the same interrupt during ...

Page 43: ...upt enable flag IE in the PSW and setting the interrupt masking level IM 2 0 to 7 b 111 If WDM 1 0 00 a watchdog interrupt occurs when the watch dog timer counts 216 cycles 5 4613 ms at 4 MHz fOSC 12 MHz fSYSCLK The WDM set tings have the following mean ings 00 216 5 46 ms 01 24 1 33 µs 10 212 0 34 ms 11 214 1 37 ms 2 Activate the watchdog timer by clearing the NWDEN bit of the CPUM regis ter Set ...

Page 44: ... for the watchdog timer The oscillator delay timer is activated when the circuit exits the STOP mode so the program must clear the WDID flag to 0 prior to entering the STOP mode It must also reclear WDID after returning to NORMAL mode For further details see section 2 6 Standby Function in the MN10200 Series Linear Addressing Version LSI User Manual Figure 2 7 Timing for Watchdog Timer Interrupt S...

Page 45: ...struction interrupts EI interrupt error interrupts XICR System Interrupt ID Interrupt detect flag 0 Interrupt undetected 1 Interrupt detected Classes 1 11 X IQ external interrupts TM timer interrupts SC serial interrupts I2C I2C interrupts OSD OSD interrupts AN A D conversion end interrupts RMC remote signal receive interrupts VBI VBI interrupts ADM address match interrupts XnICH System Interrupt ...

Page 46: ...letely so XnICH is accessible mov d0 XnICH Write to LV IE mov XnICH d0 Synchronize with the store buffer or 0x0800 psw Set the IE bit of the PSW The program does not need to clear the IE bit of the PSW to disable interrupts during interrupt servicing since the interrupt service routine has already cleared it You can replace the NOP instructions in the example above with any instruction except for ...

Page 47: ...2 x 00FC63 x 00FC64 x 00FC65 R W R W R W R W R W R W Timer 4 compare capture B interrupt control register low Timer 4 compare capture B interrupt control register high Timer 4 compare capture A interrupt control register low Timer 4 compare capture A interrupt control register high Timer 4 underflow interrupt control register low Timer 4 underflow interrupt control register high VBIICL VBIICH x 00...

Page 48: ...0FC88 x 00FC89 R W R W VBIVSYNC 1 interrupt control register low VBIVSYNC 1 interrupt control register high VBIVWICL VBIVWICH x 00FC8A x 00FC8B R W R W VBIVSYNC 2 interrupt control register low VBIVSYNC 2 interrupt control register high TM3UDICL TM3UDICH x 00FC8C x 00FC8D R W R W Timer 3 underflow interrupt control register low Timer 3 underflow interrupt control register high OSDGICL OSDGICH OSDC...

Page 49: ...ty or edge setting EXTMD is a 16 bit access register 00 Active low interrupt 01 Either edge triggered interrupt positive or negative 10 Negative edge triggered interrupt 11 Positive edge triggered interrupt The watchdog timer interrupt is provided for detecting and handling racing Normal operation is not guaranteed if the program returns after a watchdog interrupt For actions requiring returns use...

Page 50: ... writes a C to IAGR to indi cate that it detected an abnormality EIICR is an 8 bit access register IQ0ICL External Interrupt 0 Interrupt Control Register Low x 00FC48 IQ0ICL requests and verifies interrupt requests for external interrupt 0 It is an 8 bit access register Use the MOVB instruction to access it IQ0IR External interrupt 0 interrupt request flag 0 No interrupt requested 1 Interrupt requ...

Page 51: ...is an 8 bit access register Use the MOVB instruction to access it IQ1IR External interrupt 1 interrupt request flag 0 No interrupt requested 1 Interrupt requested IQ1ID External interrupt 1 interrupt detect flag 0 Interrupt undetected 1 Interrupt detected IQ1ICH External Interrupt 1 Interrupt Control Register High x 00FC4B IQ1ICH enables external interrupt 1 It is an 8 bit access register Use the ...

Page 52: ...2 It is an 8 bit access register Use the MOVB instruction to access it IQ2LV 2 0 External interrupt 2 interrupt priority level Sets the priority from 0 to 6 IQ2IE External interrupt 2 interrupt enable flag 0 Disable 1 Enable IQ3ICL External Interrupt 3 Interrupt Control Register Low x 00FC52 IQ3ICL requests and verifies interrupt requests for external interrupt 3 It is an 8 bit access register Use...

Page 53: ...s register Use the MOVB instruction to access it IQ4IR External interrupt 4 interrupt request flag 0 No interrupt requested 1 Interrupt requested IQ4ID External interrupt 4 interrupt detect flag 0 Interrupt undetected 1 Interrupt detected IQ4ICH External Interrupt 4 Interrupt Control Register High x 00FC59 IQ4ICH sets the priority level for and enables external interrupt 4 It is an 8 bit access re...

Page 54: ...ss register Use the MOVB instruction to access it The priority level for external interrupt 5 is written to the IQ4LV 2 0 field of the IQ4ICH register IQ5IE External interrupt 5 interrupt enable flag 0 Disable 1 Enable TM4CBICL Timer 4 Compare Capture B Interrupt Control Register Low x 00FC60 TM4CBICL detects and requests timer 4 compare capture B interrupts It is an 8 bit access register Use the ...

Page 55: ...ister Use the MOVB instruction to access it TM4CAIR Timer 4 compare capture A interrupt request flag 0 No interrupt requested 1 Interrupt requested TM4CAID Timer 4 compare capture A interrupt detect flag 0 Interrupt undetected 1 Interrupt detected TM4CAICH Timer 4 Compare Capture A Interrupt Control Register High x 00FC63 TM4CAICH enables timer 4 compare capture interrupts It is an 8 bit access re...

Page 56: ...w interrupts It is an 8 bit access regis ter Use the MOVB instruction to access it The priority level for timer 4 underflow interrupts is written to the TM4CBLV 2 0 field of the TM4CBICH register TM4UDIE Timer 4 underflow interrupt enable flag 0 Disable 1 Enable VBIICL VBI 1 Interrupt Control Register Low x 00FC66 VBIICL detects and requests VBI 1 interrupts It is an 8 bit access register Use the ...

Page 57: ...CBIR Timer 5 compare capture B interrupt request flag 0 No interrupt requested 1 Interrupt requested TM5CBID Timer 5 compare capture B interrupt detect flag 0 Interrupt undetected 1 Interrupt detected TM5CBICH Timer 5 Compare Capture B Interrupt Control Register High x 00FC69 TM5CBICH sets the priority level for and enables timer 5 compare capture B interrupts It is an 8 bit access register Use th...

Page 58: ... is an 8 bit access register Use the MOVB instruction to access it The priority level for timer 5 compare capture interrupts is written to the TM5CBLV 2 0 field of the TM5CBICH register TM5CAIE Timer 5 compare capture A interrupt enable flag 0 Disable 1 Enable TM5UDICL Timer 5 Underflow Interrupt Control Register Low x 00FC6C TM5UDICL detects and requests timer 5 underflow interrupts It is an 8 bi...

Page 59: ... interrupts It is an 8 bit access reg ister Use the MOVB instruction to access it VBIWIR VBI 2 interrupt request flag 0 No interrupt requested 1 Interrupt requested VBIWID VBI 2 interrupt detect flag 0 Interrupt undetected 1 Interrupt detected VBIWICH VBI 2 Interrupt Control Register High x 00FC6F VBIWICH register enables VBI 2 interrupts It is an 8 bit access register Use the MOVB instruction to ...

Page 60: ...It is an 8 bit access register Use the MOVB instruction to access it TM2UDLV 2 0 Timer 2 underflow interrupt priority level Sets the priority from 0 to 6 TM2UDIE Timer 2 underflow interrupt enable flag 0 Disable 1 Enable TM1UDICL Timer 1 Underflow Interrupt Control Register Low x 00FC72 TM1UDICL detects and requests timer 1 underflow interrupts It is an 8 bit access register Use the MOVB instructi...

Page 61: ...It is an 8 bit access register Use the MOVB instruction to access it TM0UDIR Timer 0 underflow interrupt request flag 0 No interrupt requested 1 Interrupt requested TM0UDID Timer 0 underflow interrupt detect flag 0 Interrupt undetected 1 Interrupt detected TM0UDICH Timer 0 Underflow Interrupt Control Register High x 00FC75 TM0UDICH enables timer 0 underflow interrupts It is an 8 bit access reg ist...

Page 62: ...s an 8 bit access regis ter Use the MOVB instruction to access it The priority level for remote signal receive interrupts is written to the TM2UDLV 2 0 field of the TM2UDICH register RMCIE Remote signal receive interrupt enable flag 0 Disable 1 Enable ADM3ICL Address 3 Match Interrupt Control Register Low x 00FC78 ADM3ICL detects and requests address match 3 interrupts It is an 8 bit access regist...

Page 63: ...register Use the MOVB instruction to access it ADM2IR Address match 2 interrupt request flag 0 No interrupt requested 1 Interrupt requested ADM2ID Address match 2 interrupt detect flag 0 Interrupt undetected 1 Interrupt detected ADM2ICH Address 2 Match Interrupt Control Register High x 00FC7B ADM2ICH enables address match 2 interrupts It is an 8 bit access regis ter Use the MOVB instruction to acc...

Page 64: ... access register Use the MOVB instruction to access it The priority level for address match 1 interrupts is written to the ADM3LV 2 0 field of the ADM3ICH register ADM1IE Address match 1 interrupt enable flag 0 Disable 1 Enable ADM0ICL Address 0 Match Interrupt Control Register Low x 00FC7E ADM0ICL detects and requests address match 0 interrupts It is an 8 bit access register Use the MOVB instruct...

Page 65: ...s register Use the MOVB instruction to access it ANIR A D conversion end interrupt request flag 0 No interrupt requested 1 Interrupt requested ANID A D conversion end interrupt detect flag 0 Interrupt undetected 1 Interrupt detected ANICH A D Conversion End Interrupt Control Register High x 00FC81 ANICH sets the priority level for and enables A D conversion end inter rupts It is an 8 bit access re...

Page 66: ...an 8 bit access reg ister Use the MOVB instruction to access it The priority level for serial 0 transmission end interrupts is written to the ANLV 2 0 field of the ANICH register SCT0IE Serial 0 transmission end interrupt enable flag 0 Disable 1 Enable SCR0ICL Serial 0 Reception End Interrupt Control Register Low x 00FC84 SCR0ICL detects and requests serial 0 reception end interrupts It is an 8 bi...

Page 67: ... an 8 bit access register Use the MOVB instruction to access it VBIVIR VBIVSYNC 1 interrupt request flag 0 No interrupt requested 1 Interrupt requested VBIVID VBIVSYNC 1 interrupt detect flag 0 Interrupt undetected 1 Interrupt detected VBIVICH VBIVSYNC 1 Interrupt Control Register High x 00FC89 VBIVICH sets the priority level for and enables VBIVSYNC 1 inter rupts It is an 8 bit access register Us...

Page 68: ... Use the MOVB instruction to access it The priority level for VBIVSYNC 2 interrupts is written to the VBIVLV 2 0 field of the VBIVICH register VBIVWIE VBIVSYNC 2 interrupt enable flag 0 Disable 1 Enable TM3UDICL Timer 3 Underflow Interrupt Control Register Low x 00FC8C TM3UDICL detects and requests timer 3 underflow interrupts It is an 8 bit access register Use the MOVB instruction to access it TM...

Page 69: ...ccess register Use the MOVB instruction to access it OSDGIR OSD graphics interrupt request flag 0 No interrupt requested 1 Interrupt requested OSDGID OSD graphics interrupt detect flag 0 Interrupt undetected 1 Interrupt detected OSDGICH OSD Graphics Interrupt Control Register High x 00FC91 OSDGICH sets the priority level for and enables OSD graphics inter rupts It is an 8 bit access register Use t...

Page 70: ...nstruction to access it The priority level for OSD text interrupts is written to the OSDGLV 2 0 field of the OSDGICH register OSDCIE OSD text interrupt enable flag 0 Disable 1 Enable SCT1ICL Serial 1 Transmission End Interrupt Control Register Low x 00FC98 SCT1ICL detects and requests serial 1 transmission end interrupts It is an 8 bit access register Use the MOVB instruction to access it SCT1IR S...

Page 71: ...ccess register Use the MOVB instruction to access it SCT1IR Serial 1 reception end interrupt request flag 0 No interrupt requested 1 Interrupt requested SCT1ID Serial 1 reception end interrupt detect flag 0 Interrupt undetected 1 Interrupt detected SCR1ICH Serial 1 Reception End Interrupt Control Register High x 00FC9B SCR1ICH enables serial 1 reception end interrupts It is an 8 bit access registe...

Page 72: ...ested 1 Interrupt requested I2CID I2C interrupt detect flag 0 Interrupt undetected 1 Interrupt detected I2CICH I2C Interrupt Control Register High x 00FC9D I2CICH enables I2 C interrupts It is an 8 bit access register Use the MOVB instruction to access it The priority level for I2 C interrupts is written to the SCT1LV 2 0 field of the SCT1ICH register I2CIE I2 C interrupt enable flag 0 Disable 1 E...

Page 73: ...PUM controls transitions between NORMAL and SLOW modes and from NORMAL and SLOW modes to the standby modes A normal reset or an interrupt wakes the MCU from a standby mode Note that you cannot invoke the STOP mode from NORMAL mode You can only enter STOP from the SLOW mode Figure 3 1 CPU State Changes NORMAL Mode Clock to CPU 24 MHz System clock 12 MHz CPU and PLL on SLOW Mode Clock to CPU 4 MHz S...

Page 74: ... switch the CPU from SLOW to NORMAL mode system clock 12 MHz Below is an example routine for exiting SLOW mode You should run this routine immediately after power up Example 3 1 Exiting SLOW Mode MOV x FC00 A1 MOV A1 D0 Read CPUM register AND x FFFD D0 Invoke IDLE mode MOV D0 A1 MOV A1 D0 Read CPUM register AND x FFF0 D0 Invoke NORMAL mode MOV D0 A1 The OSD cannot display in SLOW mode Because the ...

Page 75: ...f the bits shown in table 3 1 to disable all of these functions Disable all functions in the NORMAL mode except the PLL circuit which you can only shut down once you have entered the SLOW mode Using OSDX clock both an LC blocking oscillator and external source OSDXI and OSDXO must be set to port P46 P45 and output H before invoking STOP mode To allow the MCU to exit the STOP or HALT mode on reset ...

Page 76: ...r more information Table 3 1 Peripheral Function On Off Switches Block Name Description Bit Name Address Operation Reset Value OSD OSD block control OSDPOFF PCNT0 x 00FF90 bit 7 0 OSD block off 1 OSD block enabled 0 OSD function control OSD OSD1 x 007F06 bit 10 0 OSD function off 1 OSD function on 0 OSD register R W control OSDREG E PCNT2 x 00FF92 bit 0 0 OSD register R W off 1 OSD register R W en...

Page 77: ...ast 1 Slow STOP STOP mode request CPU operating state control See table 3 2 HALT HALT mode request CPU operating state control See table 3 2 OSC 1 0 Oscillator control See table 3 2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NW DEN OSC ID STOP HALT OSC1 OSC0 Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R R R R R R R R R R R R W R W R W R W Table 3 2 CPU Mode Bit Settings STOP HALT OSC1 OSC0 CPU Mo...

Page 78: ...me a clock BOSC of 24 MHz The 8 bit timers are cascadable into true 16 bit timers For instance if you cascade timers 0 and 1 timer 0 sends cascaded output to timer 1 The result is true 16 bit division rather than two successive 8 bit divisions Figure 4 1 Timer Configuration Examples Note BOSC 24 MHz Figure 4 2 Block Diagram of 8 Bit Timers Cascading Connections 8 bit x 4 16 bit 8 bit 8 bit 8 bit 8...

Page 79: ...it Interrupt source s Timer 0 underflow Timer 1 underflow Timer 2 underflow Timer 3 underflow Interval timer function Event counter function Clock source for 16 bit timer Timer output function TM0O signal TM1O signal Serial interface transfer clock source A D conversion trigger function Clock sources 0 BOSC 4 BOSC 4 BOSC 4 BOSC 4 1 BOSC 64 BOSC 64 BOSC 256 BOSC 256 2 BOSC 512 Cascade connection Ca...

Page 80: ...plexer 0 1 2 3 Timer 0 underflow interrupt Underflow Reload Timer 0 base register TM0BR TM0LD TM0EN TM0S0 TM0S1 Load Count 8 Timer 0 binary counter TM0BC 8 8 Data bus 8 1 2 Reset P2MD7 P2DIR7 setting TM0O pin FE11 FE01 TM1MD FE21 0 1 2 3 Underflow Reload Timer 1 base register TM1BR TM1LD TM1EN TM1S0 TM1S1 Load Count 8 Timer 1 binary counter TM1BC 8 8 8 Data bus BOSC 4 BOSC 64 Cascade from timer 0 ...

Page 81: ...terrupt 0 1 2 3 Underflow Reload Timer 2 base register TM2BR TM2LD TM2EN TM2S0 TM2S1 Load Count 8 Timer 2 binary counter TM2BC 8 8 8 Data bus BOSC 4 BOSC 256 Cascade from timer 1 BOSC 512 Multiplexer FE13 FE03 TM3MD FE23 Timer 3 underflow interrupt 0 1 2 3 Underflow Reload Timer 3 base register TM3BR TM3LD TM3EN TM3S0 TM3S1 Load Count 8 Timer 2 binary counter TM3BC 8 8 8 Data bus BOSC 4 BOSC 256 C...

Page 82: ...miconductor Development Company 81 Panasonic 4 4 8 Bit Timer Timing Figure 4 7 Event Timer Input Timing 8 Bit Timers Figure 4 8 Clock Output and Interval Timer Timing 8 Bit Timers Load value TMnIO input BC value Time Load value TMnIO input 1 TMnIO output 2 BC value Time Interrupt ...

Page 83: ...able flag IE of the processor status word PSW to 1 2 Disable timer 0 counting in the timer 0 mode register TM0MD This step is unnecessary immediately after a reset since TM0MD resets to 0 TM0MD example x 00FE20 TM2UDICH TM0UDICL and TM0UDICH are 8 bit access registers Use the MOVB instruction to access them 3 Cancel all existing interrupt requests and enable timer 0 underflow inter rupts To do thi...

Page 84: ... the bank and linear address ing versions of the MN102 series it was necessary to set TM0EN and TM0LD to 0 between steps 5 and 6 to ensure stable operation This is unnecessary in the high speed linear addressing version 6 Set TM0LD to 0 and TM0EN to 1 This starts the timer Counting begins at the start of the next cycle When the binary counter reaches 0 and loads the value x 03 from the base regist...

Page 85: ...this example set the TM2UDIE bit to 1 set the TM2UDIR bit of TM2UDICL to 0 set the TM1UDIE bit of TM1UDICH to 0 and set the TM1UDIR bit of TM1UDICL to 0 Note that you set the priority level for both timer 1 and 2 interrupts in the timer 2 interrupt control register From this point on an interrupt request is generated whenever timer 2 underflows Timer 1 underflows are unused Figure 4 11 Configurati...

Page 86: ...ary counter 4 Set the TM1LD bit of the TM1MD register and theTM2LD bit of the TM2MD register to 1 This loads the value in the base register to the binary counter At the same time select the clock source as the BOSC 4 for timer 1 and cascade to timer 1 for timer 2 Write to TMnS 1 0 TM1MD example x 00FE21 Bit 7 6 5 4 3 2 1 0 TM2UD LV2 TM2UD LV1 TM2UD LV0 TM2UD IE Setting 0 1 0 0 0 0 0 1 Bit 7 6 5 4 ...

Page 87: ... timers Counting begins at the start of the next cycle When both the timer 1 and 2 binary counters reach 0 and loads the values from the base registers in preparation for the next count a timer 2 underflow inter rupt request is sent to the CPU The timer 1 interrupt is unused Access TM2MD and TM1MD with a 16 bit write using the MOV instruction or set the two registers consecutively begin ning with ...

Page 88: ...urce 3 Table 4 2 8 Bit Timer Control Registers Register Address R W Description Timer 0 TM0BC x 00FE00 R Timer 0 binary counter TM0BR x 00FE10 R W Timer 0 base register TM0MD x 00FE20 R W Timer 0 mode register Timer 1 TM1BC x 00FE01 R Timer 1 binary counter TM1BR x 00FE11 R W Timer 1 base register TM1MD x 00FE21 R W Timer 1 mode register Timer 2 TM2BC x 00FE02 R Timer 2 binary counter TM2BR x 00FE...

Page 89: ...e This prevents PWM signal losses and minimizes waveform distortion during timing changes Underflow interrupts can only occur during down counting Timers 5 and 6 can serve as interval timers event counters in clock oscillation mode one or two phase PWMs dual capture inputs dual two phase encoders one shot pulse generators and external count direction controllers The clock source can be the interna...

Page 90: ... compare B match Timer 4 capture B Timer 5 underflow Timer 5 compare A match Timer 5 capture A Timer 5 compare B match Timer 5 capture B Clock sources Timer 0 underflow Timer 1 underflow TM4IB signal 4x two phase encoder TM4IA and TM4IB signals 1x two phase encoder TM4IA and TM4IB signals Timer 0 underflow Timer 1 underflow TM5IB signal 4x two phase encoder TM5IA and TM5IB signals 1x two phase enc...

Page 91: ... TM4CA TM4CAX TM4CB TM4CBX TM4MD Capture Match Match CLK CLR T T Q Q Q R R R R S LOAD Capture TGE EN ECLR ASEL LP S UD MD LD ONE U D control TM4IA pin TM4IOA pin P2MD6 P2DIR6 setting TM4IOB pin P2MD5 P2DIR5 setting BOSC 4 Selector Controller TM5IC pin Timer 0 underflow Timer 1 underflow TM5IB pin TM5IB pin TM5BC TM5CA TM5CAX TM5CB TM5CBX TM5MD Capture Match Match CLK CLR T T Q Q Q R R R R S LOAD C...

Page 92: ...4 18 Single Phase PWM Output Timing with Data Change 16 Bit Timers Figure 4 19 Two Phase PWM Output Timing 16 Bit Timers Figure 4 20 One Shot Pulse Output Timing 16 Bit Timers CA TMnIOA TMnOA BC value Time CB New value written to CCRB Change reflected in next clock cycle CA BC value Time CB TMnOB TMnOA CA TMnOA BC value Time TMnIB ...

Page 93: ...al 92 Panasonic Figure 4 21 External Count Direction Control Timing 16 Bit Timers Figure 4 22 Event Timer Input Timing 16 Bit Timers Figure 4 23 Single Phase Capture Input Timing 16 Bit Timers TMnIB TMnIA CA BC value Time TMnIB BC value Time 0033 Example 5A87 Example TMnIB TMnIA TMnCA TMnCB FFFF BC value Time ...

Page 94: ...ompany 93 Panasonic Figure 4 24 Two Phase Capture Input Timing 16 Bit Timers Figure 4 25 Two Phase 4x Encoder Timing 16 Bit Timers Figure 4 26 Two Phase 1x Encoder Timing 16 Bit Timers TMnIB TMnIA TMnCA 0033 Example 5A87 Example TMnCB FFFF BC value Time TMnIB TMnIA BC value Time TMnIB TMnIA BC value Time ...

Page 95: ...e register TM4MD Disable timer 4 counting and interrupts Select up counting Select TM4IB as the clock source TM4MD example x 00FE80 2 Set the divide by ratio for timer 4 To divide the TM4IB input signal by 5 write x 0004 to timer 4 compare capture register A TM4CA The valid range for TM4CA is x 0001 to x FFFE A Chip Level B Block Level Figure 4 27 Block Diagram of Event Counter Using Timer 4 TM4IB...

Page 96: ...e TM4CBIR bit of TM4CBICL to 0 set the TM4CAIE bit of TM4CAICH to 1 and set the TM4CAIR bit of TM4CAICL to 0 From this point on an interrupt request is generated whenever a timer 4 capture A or capture B event occurs Timer 4 can operate as an event counter but timer 4 does not operate in STOP mode when BOSC is off If you use an external clock it must be synchronized to BOSC This means that the fre...

Page 97: ... Set the P2MD 13 12 bits of the port 2 output mode register P2MD to b 01 selecting the TM4IOA pin and set the P2DIR6 bit of the port 2 I O control register P2DIR to 1 selecting output direction This step selects the TM4OA pin P26 as the timer output port P2MD example x 00FFF4 A Chip Level B Block Level Figure 4 29 Block Diagram of Single Phase PWM Output Using Timer 4 TM4OA P3 P6 PC P4 P5 CORE Int...

Page 98: ...to TM4CAX The contents of TM4CA are loaded to TM4CAX when TM4BC TM4CAX However since TM4CAX is undefined or x 0000 before this operation starts this initial dummy write prevents timing errors 5 Write a dummy data word of any value to TM4CBX In double buffer mode TM4CB is compared to TM4CBX The contents of TM4CB are loaded to TM4CBX when TM4BC TM4CBX However since TM4CBX is undefined or x 0000 befo...

Page 99: ...mer 4 does not operate in STOP mode when BOSC is off If you use an external clock it must be synchronized to BOSC In this procedure you set the cycle x 0001 to x FFFE in the TM4CA register and the duty in the TM4CB register When the contents of TM4BC match those of the TM4CB register the S R flip flop resets at the beginning of the next cycle Please note the following When 1 TM4CB TM4CA TM4OA outp...

Page 100: ... only occur if the TM4CB setting is from 0 to less than TM4CA This is because when TM4CB TM4CA TM4BC never matches TM4CB Figure 4 30 Single Phase PWM Output Timing Timer 4 Write to TM4MD TM4EN TM4BC BOSC 4 CLRBC4 S4 R4 TM4OA Interrupts 0 1 2 3 4 0 0 1 2 3 4 0 1 2 3 4 0 1 2 3 AB AB AB B A B A B B A 1 TMCB 4 All 0s S4 R4 TM4OA Interrupts 2 TMCB 2 A A A S4 R4 TM4OA Interrupts 0s on first cycle since ...

Page 101: ...imers 4 and 5 provide a double buffer mode In this mode no matter what the timing of a TMnCB change the duty change does occur until the beginning of the next cycle and no signals are lost Performance is assured even when the output switches from all 1s to all 0s see the double buffering section of figure 4 31 below For this reason you must always use double buffer mode for PWM waveform output Use...

Page 102: ... 2 output mode register P2MD to b 01 selecting the TM4IOA pin set the P2MD 11 10 bits to b 01 selecting the TM4IOB pin and set the P2DIR 6 5 bits of the port 2 I O control register P2DIR to b 11 selecting output direction This step selects the TM4OA P26 and TM4OB P25 pins as the timer output ports P2MD example x 00FFF4 A Chip Level B Block Level Figure 4 32 Block Diagram of Two Phase PWM Output Us...

Page 103: ...binary counter At the same time select the clock source as BOSC 4 by writing b 00 to TM0S 1 0 TM0MD example x 00FE20 In the bank and linear address ing versions of the MN102 series it was necessary to set TM0EN and TM0LD to 0 between steps 3 and 4 to ensure stable operation This is unnecessary in the high speed linear addressing version 4 Set TM0LD to 0 and TM0EN to 1 This starts the timer Countin...

Page 104: ...ue to TM4CAX In double buffer mode TM4CA is compared to TM4CAX The contents of TM4CA are loaded to TM4CAX when TM4BC TM4CAX However since TM4CAX is undefined or x 0000 before this operation starts this initial dummy write prevents timing errors 5 Write a dummy data word of any value to TM4CBX In double buffer mode TM4CB is compared to TM4CBX The contents of TM4CB are loaded to TM4CBX when TM4BC TM...

Page 105: ...the phase difference in the TM4CB register When the contents of TM4BC match those of the TM4CB register T flip flop B reverses at the beginning of the next cycle When the contents of TM4BC match those of the TM4CA register T flip flop A reverses and TM4BC resets at the beginning of the next cycle The circuitry is configured so that there are no waveform errors even when the output is always high o...

Page 106: ... signals are lost Per formance is assured even when the output switches from all 1s to all 0s see the double buffering section of figure 4 34 below For this reason you must always use double buffer mode for PWM waveform output Use single buffer mode only in applications that are unaffected by this issues Figure 4 34 Two Phase PWM Output Timing with Dynamic Duty Changes Timer 4 0 1 2 3 4 0 0 1 2 3 ...

Page 107: ...er TM4MD Disable timer 4 counting and interrupts Select up counting Set the TM4NLP bit to 0 to select looped counting from 0 to x FFFF Select BOSC 4 as the clock source TM4MD example x 00FE80 2 Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0 This enables TM4BC and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first ...

Page 108: ...culat ing the signal width even when TM3CA is the larger value 2 Calculate the number of cycles the TM4IA signal stays high Save the con tents of TM4CA and TM4CB to the data registers then subtract the contents of TM4CA from the contents of TM4CB Since TM4LP is set to 0 the dif ference will be the correct value even if TM4CA is greater than TM4CB Timer 4 can input a single phase capture signal You...

Page 109: ...rom the contents of TMnCB To set up timer 0 1 Disable timer 0 counting in the timer 0 mode register TM0MD This step is unnecessary immediately after a reset since TM0MD resets to 0 TM0MD example x 00FE20 2 Set the divide by ratio for timer 0 To divide BOSC 4 by two write x 01 to the timer 0 base register TM0BR The valid range for TM0BR is 0 to 255 A Chip Level B Block Level Figure 4 37 Block Diagr...

Page 110: ...mer 4 mode register TM4MD Disable timer 4 counting and interrupts Select up counting Set the TM4NLP bit to 0 to select looped counting from 0 to x FFFF Select timer 0 underflow as the clock source TM4MD example x 00FE80 2 Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0 This enables TM4BC and the S R flip flop This step ensures stable opera tion If it is omitted the binary coun...

Page 111: ...even if TM4CA is greater than TM4CB Timer 4 can input a two phase capture signal You must select up counting Timer 4 does not operate in STOP mode when BOSC is off If you use an external clock it must be synchronized to BOSC TM4CA captures the count on the rising edge of TM4IA and TM4CB captures the count on the rising edge of TM4IB A timer 4 capture B interrupt occurs when TM4CB captures the coun...

Page 112: ...ferent values for A and B interrupts TM5LP must be 0 A Chip Level B Block Level Figure 4 39 Block Diagram of 4x Two Phase Capture Input Using Timer 5 Figure 4 40 Configuration Example 1 of 4x Two Phase Capture Input Using Timer 5 Figure 4 41 Configuration Example 2 of 4x Two Phase Capture Input Using Timer 5 TM5IA TM5IB P3 P5 CORE Interrupts Timers 0 3 Timers 4 5 ROM RAM Bus Controller Serial I Fs...

Page 113: ...D register to 1 and the TM5EN bit to 0 This enables TM5BC and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 5 Set TM5NLD and TM5EN to 1 This starts the timer Counting begins at the start of the next cycle To enable timer 5 capture B interrupts Cancel all existing inter...

Page 114: ...s off If you use an external clock it must be synchronized to BOSC Table 4 4 shows the count direction for the timing diagram in figure 4 42 In down counting when the binary counter reaches 0 it loops to the value in TM5CA An interrupt B occurs when the contents of TM5BC match those of TM5CB Table 4 4 Count Direction for 4x Two Phase Encoder Timing Example Up Counting Down Counting TM5IA 1 0 0 1 T...

Page 115: ...ferent values for A and B interrupts TM5LP must be 0 A Chip Level B Block Level Figure 4 43 Block Diagram of 1x Two Phase Capture Input Using Timer 5 Figure 4 44 Configuration Example 1 of 1x Two Phase Capture Input Using Timer 5 Figure 4 45 Configuration Example 2 of 1x Two Phase Capture Input Using Timer 5 TM5IA TM5IB P3 P5 CORE Interrupts Timers 0 3 Timers 4 5 ROM RAM Bus Controller Serial I Fs...

Page 116: ...D register to 1 and the TM5EN bit to 0 This enables TM5BC and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 5 Set TM5NLD and TM5EN to 1 This starts the timer Counting begins at the start of the next cycle To enable timer 5 capture B interrupts Cancel all existing inter...

Page 117: ...SC is off If you use an external clock it must be synchronized to BOSC Table 4 5 shows the count direction for the timing diagram in figure 4 46 In down counting when the binary counter reaches 0 it loops to the value in TM5CA An interrupt B occurs when the contents of TM5BC match those of TM5CB Table 4 5 Count Direction for 1x Two Phase Encoder Timing Example Up Counting Down Counting TM5IA TM5IB...

Page 118: ...ter P4DIR to 1 selecting output direction This step selects the TM5OA pin P42 as the timer output port P4MD example x 00FFF8 P2DIR example x 00FFE4 A Chip Level B Block Level Figure 4 47 Block Diagram of One Shot Pulse Output Using Timer 5 TM5OA TM5IB P3 P5 CORE Interrupts Timers 0 3 Timers 4 5 ROM RAM Bus Controller Serial I Fs ADC P2 P6 P4 up down TM5BC Timer 5 TM5CA TM5CB BOSC 4 TM5IB T Q T Q R...

Page 119: ...f the TM5MD register to 1 and the TM5EN bit to 0 This enables TM5BC and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 5 On the falling edge of the TM5IB signal the hardware sets the TM5EN bit to 1 This means that counting begins at the start of the next cycle after the...

Page 120: ...t and S5 set signals are not asserted After the count starts when it changes from 0 to 1 the S5 signal is asserted This sets the TM5OA signal high and it outputs the one shot pulse When the count reaches 3 TM5BC resets changing from 3 to 0 and the R5 signal is asserted causing the TM5OA signal to go low Because the TM5ONE bit of the TM5MD register is 1 and the TM5EN bit is reset the count stops Th...

Page 121: ...tion up or down An interrupt occurs when the counter reaches a preset value A Chip Level B Block Level Figure 4 49 Block Diagram of External Count Direction Control Using Timer 5 Figure 4 50 Configuration Example of External Count Direction Control Using Timer 5 TM5IA P3 P5 CORE Interrupts Timers 0 3 Timers 4 5 ROM RAM Bus Controller Serial I Fs ADC P2 P6 P4 up down Interrupt B TM5BC Timer 5 TM5CA...

Page 122: ...ster to 1 and the TM5EN bit to 0 This enables TM5BC and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 5 Set TM5NLD and TM5EN to 1 This starts the timer Counting begins at the start of the next cycle To enable timer 5 capture B interrupts Cancel all existing interrupt r...

Page 123: ...unt direction is determined at the opposite edge from the count edge at the source clock transition occurring in the middle of the count cycle Timer 5 does not operate in STOP mode when BOSC is off If you use an external clock it must be synchronized to BOSC Figure 4 51 shows an example timing chart In this example an interrupt occurs when the timer switches from down to up counting Figure 4 51 Ex...

Page 124: ...unting Since the TM5IC signal will reset the counter asynchronously set the TM5ECLR bit to 1 Select BOSC 4 as the clock source TM5MD example x 00FE90 2 Set the value to which timer 5 will loop valid settings x 0001 to x FFFF For TM5BC to count from x 0000 to x 1FFF for instance write x 1FFF to TM5CA A Chip Level B Block Level Figure 4 52 Block Diagram of External Reset Control Using Timer 5 TM5IC ...

Page 125: ...nal is high timer 5 will be reset asynchronously This is an easy way to synchronize the microcontroller operation with an external event You can use it to adjust motor speed or to initialize the timers through the hardware Timer 5 does not operate in STOP mode when BOSC is off If you use an external clock it must be synchronized to BOSC Figure 4 53 shows an example timing chart Bit 15 14 13 12 11 ...

Page 126: ...imer 5 binary counter TM5CA x 00FE94 R W Timer 5 compare capture register A TM5CAX x 00FE96 Timer 5 compare capture register set AX TM5CB x 00FE98 R W Timer 5 compare capture register B TM5CBX x 00FE9A Timer 5 compare capture register set BX Note TM4CAX TM4CBX TM5CAX and TM5CBX are virtual registers used only in double buffer mode during PWM output They do not exist in the hardware and are not rea...

Page 127: ... TMnCA TMnMD 1 0 TMnCA and TMnCB operating mode select 00 Compare register single buffer 01 Compare register double buffer 10 Capture register TMnIOA high capture A TMnIOA low capture B 11 Capture register TMnIOA high capture A TMnIOB high captureB TMnECLR Timer n BC external clear 0 Don t clear 1 Clear TMnBC asynchronously when the TMnIC signal goes high TMnLP Timer n BC loop select 0 0000 FFFF 1...

Page 128: ... Tx end interrupt Rx end interrupt Tx end interrupt Rx end interrupt Table 5 1 Serial Interface Functions and Features Function Feature Synchronous Serial Mode UART Mode I2C Mode Parity None 0 1 even or odd Can be master trans mitter or receiver No collision detection for start sequence Character length 7 bit or 8 bit Transfer bit order LSB or MSB first programmable 8 bit only LSB first Clock sour...

Page 129: ...x or full duplex UART transfers 5 3 3 I2 C Mode Connection The serial interfaces can connect to I2 C slave transmitters or receivers For this mode always pull up the SBO and SBT pins to VDD Either connect a pullup resistor externally or turn on the internal one by setting the PPLU register A Simplex Connection B Full Duplex Connection Figure 5 2 Synchronous Serial Mode Connections A Simplex Connec...

Page 130: ...r the UART mode Table 5 2 shows the baud rate settings when BOSC 24 MHz 5 5 Serial Interface Timing 5 5 1 Synchronous Serial Mode Timing In these timing charts the character length is 8 bits and there is parity Table 5 2 Example Baud Rate Settings for the UART Mode Baud Rate Timer 0 1 Divide by Ratio 19200 9600 4800 2400 1200 600 300 39 78 156 313 625 1250 2500 Figure 5 5 Synchronous Serial Transm...

Page 131: ...s the parity is none and the stop bit is 2 bit Figure 5 6 Synchronous Serial Reception Timing Figure 5 7 UART Transmission Timing Figure 5 8 UART Reception Timing SBI SBT RXBUSY Rx interrupt RXA 1 when Rx data in Data read Rx b0 b1 b2 b3 b4 b5 b6 b7 PTY SBO Data write TXBUSY Tx interrupt ST b0 b1 b2 b3 b4 b5 b6 b7 SP SP Tx SBI RXBUSY Rx interrupt RXA 1 when Rx data in Data read ST b0 b1 b2 b3 b4 b...

Page 132: ... next data byte is loaded Data transmission starts when the CPU writes data to the SC0TRB register The transmission start is synchronized to timer 0 underflow An interrupt occurs when transmission ends and the next data byte is written to SC0TRB If the application does not use interrupts it must poll the SC0TBY flag of the SC0STR register It can write the transmission data when SC0TBY is 0 To set ...

Page 133: ...ransmission To enable serial 0 transmission end interrupts Cancel all existing interrupt requests Next set the interrupt priority level of 5 in the ANLV 2 0 bits of the ANICH register set the SCT0IE bit of SCT0ICH to 1 and set the SCT0IR bit of SCT0ICL to 0 From this point on an interrupt request is generated whenever a serial data transmission ends ANICH example x 00FC81 SCT0ICL example x 00FC82 ...

Page 134: ... program branches to the interrupt service rou tine The routine must determine the interrupt group then clear the interrupt request flag 3 Write the next data byte to SC0TRB Once the write is complete transmis sion begins in 1 or 2 cycles of the transfer clock timer 0 underflow Figure 5 10 shows an example timing chart Figure 5 10 UART Transmission Timing Serial Interface 0 TC0 underflow 1 8 SC0TR...

Page 135: ...0 underflow x 1 8 as the serial port 0 clock source Select synchronous serial mode odd parity 8 bit data length and LSB first output SC0CTR example x 00FD80 To enable serial 0 transmission end interrupts Cancel all existing interrupt requests Next set the interrupt priority level of 5 in the ANLV 2 0 bits of the ANICH register set the SCR0IE bit of SCR0ICH to 1 and set the SCR0IR bit of SCR0ICL to...

Page 136: ... or eight Always select divide by eight for UART transactions For a baud rate of 19 200 since BOSC 4 6 MHz 6 MHz 39 8 19230 77 bps This means that the timer 1 underflow must be divided by 39 To set timer 1 1 Disable timer 1 counting in the timer 1 mode register TM1MD This step is unnecessary immediately after a reset since TM1MD resets to 0 TM1MD example x 00FE21 2 Set the divide by ratio for time...

Page 137: ...nd TM1LD to 0 between steps 3 and 4 to ensure stable operation This is unnecessary in the high speed linear addressing version 4 Set TM1LD to 0 and TM1EN to 1 This starts the timer Counting begins at the start of the next cycle When the binary counter reaches 0 and loads the value x 26 from the base register in preparation for the next count a timer 1 underflow occurs The serial interface operates...

Page 138: ...ion SC0TEN and SC0REN 1 and disable transmission breaks SC0BRE 0 Select the timer 0 underflow rate divided by 8 as the clock source SC0CTR example x 00FD80 To set up the start sequence Reception must be enabled for the circuit to detect a start sequence Write a 1 to the SC0IIC bit of the SC0CTR register to signal the start sequence The SBO0 pin output immediately goes low Read SC0STR to verify tha...

Page 139: ...gnalling the stop sequence The SC0ISP flag of SC0STR becomes 1 The SC0IST and SC0ISP flags are both cleared by a write to or read from the serial port 0 transmit receive buffer Figure 5 13 shows an example timing chart Figure 5 13 Master Transmitter Timing in I2 C Mode with ACK b7 b6 b5 b4 b3 b2 b1 b0 b6 b5 b4 b3 b2 b1 b0 ACK b7 ACK Tx interrupt request Stop detection bit 1 Start detection bit 1 I...

Page 140: ...one if there is no ACK signal 1 During the interrupt service routine for the serial transmission end enable reception by setting the SC0REN bit of SC0CTR to 1 2 Select ACK output of 1 To set up data reception 1 Write a dummy data bit x FF to the serial port 0 transmit receive buffer This sets the SBO0 signal high and initiates the master receiver mode 2 During the service routine for the serial re...

Page 141: ...quence output Do not change this bit during transmission or reception 0 Output stop sequence upon 1 to 0 transition 1 Output start sequence upon 0 to 1 transition SCnPTL Serial port n protocol select 0 UART 1 Synchronous serial or I2 C SCnOD Serial port n bit order This bit must be set to 0 during 7 bit transmission 0 LSB first 1 MSB first Table 5 3 Serial Interface Control Registers Register Addr...

Page 142: ...1 underflow 1 8 SC0TRB SC1TRB Serial Port n Transmit Receive Buffer x 00FD82 x 00FD88 Data transmission begins when the CPU writes data to SCnTRB The CPU retrieves the data by reading SCnTRB SCnTRB has two respec tive buffers for transmission and for reception The buffers for reception is consist of two buffers and the received data is set to SCnTRB after the reception ends and held until that of ...

Page 143: ... n framing error A framing error occurs when a 0 is received during stop bit transfer Fram ing error data is updated each time the stop bit is received 0 No error 1 Framing error occurred SCnPE Serial port n parity error A parity error occurs when the received parity bit is 1 and the parity setting is 0 when the received parity bit is 0 and the parity setting is 1 when the received parity bit is o...

Page 144: ...UF AN4BUF AN5BUF AN6BUF AN7BUF AN8BUF AN9BUF AN10BUF AN11BUF M U X Table 6 1 ADC Functions and Features Function Feature Description Sample and hold Embedded Conversion time 4 µs per channel when BOSC 24 MHz Clock sources Programmable to BOSC divided by 8 or 16 Operating modes 46 operating modes four types 1 Single conversion of one input channel 0 1 2 3 4 5 6 7 8 9 10 or 11 Single conversion of m...

Page 145: ...ou set the clock source to BOSC 8 the conversion time is BOSC 96 cycles Figure 6 2 ADC Block Diagram Figure 6 3 ADC Timing VDD VSS ANCTR BOSC A D interrupt request AN11BUF AN0BUF ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 ADIN5 ADIN6 ADIN7 ADIN8 ADIN9 ADIN10 ADIN11 M U X Shift register for state information Divider INC Interrupt generated Compare Data registers 8 bit x 12 128 64 32 16 8 4 2 1 1 ANNCH AN1CH Sto...

Page 146: ...nverts multiple consecutive ADIN input signals a single time An interrupt occurs when the conversion sequence ends Load 0s to the AN1CH 3 0 field of the ADC control register ANCTR then load the number of the final channel in the sequence to the ANNCH 3 0 field The sequence always begins with channel 0 When the software starts the conversion write a 0 to the ANTC bit disabling conversion start at t...

Page 147: ... An interrupt occurs each time the conversion sequence ends Load 0s to the AN1CH 3 0 field of the ADC control register ANCTR then load the number of the final channel in the sequence to the ANNCH 3 0 field The sequence always begins with channel 0 When the software starts the conversion write a 0 to the ANTC bit disabling conversion start at timer 1 underflow then write a 1 to ANEN If ANTC 1 ANEN ...

Page 148: ...mple x 00FF00 When the software controls the conversion start it must set the ANEN flag to 1 2 Set ANEN to 1 to start conversion Conversion starts on the first rising edge of the ADC clock after ANEN is set The conversion time is 12 cycles of the ADC clock When BOSC 24 MHz this is 4 0 µs or 4 0µs 4 3 µs after ANEN is set The ADC can also generate an interrupt when the conversion ends once the data...

Page 149: ...d the ADC converts the voltages to 8 bit digital values It writes the results to the registers periodically each time timer 1 underflows Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ANn BUF7 ANn BUF6 ANn BUF5 ANn BUF4 ANn BUF3 ANn BUF2 ANn BUF1 ANn BUF0 Figure 6 9 Timing of Software Controlled Single Channel A D Conversion Figure 6 10 Multiple Channel A D Conversion 1 2 3 4 10 11 12 VALID ADIN6 conve...

Page 150: ...for TM1BR is 1 to 255 TM1BR example x 00FE11 Do not change the clock source once you have selected it Selecting the clock source while you set up the count operation control will corrupt the value in the binary counter 2 Set the TM1LD bit of the TM1MD register to 1 and the TM1EN bit to 0 This loads the value in the base register to the binary counter TM1MD example x 00FE21 3 Set TM1LD to 0 and TM1...

Page 151: ...ess R W Description ANCTR x 00FF00 R W ADC control register AN0BUF x 00FF08 R ADIN0 conversion data buffer AN1BUF x 00FF0A R ADIN1 conversion data buffer AN2BUF x 00FF0C R ADIN2 conversion data buffer AN3BUF x 00FF0E R ADIN3 conversion data buffer AN4BUF x 00FF10 R ADIN4 conversion data buffer AN5BUF x 00FF12 R ADIN5 conversion data buffer AN6BUF x 00FF14 R ADIN6 conversion data buffer AN7BUF x 00...

Page 152: ...vert ADIN8 0010 Convert ADIN2 1001 Convert ADIN9 0011 Convert ADIN3 1010 Convert ADIN10 0100 Convert ADIN4 1011 Convert ADIN11 0101 Convert ADIN5 1100 1111 Reserved 0110 Convert ADIN6 ANEN Conversion start busy flag 0 No conversion in progress 1 Conversion in progress ANTC Conversion start at timer 1 underflow 0 Disable 1 Enable ANCTR5 Always set this bit to 0 ANCK 1 0 Clock source select 00 Reser...

Page 153: ...ed to get the accurancy of convension 1 Impedance of analog input terminal must be below 8kΩ 2 When impedance of analog input terminal is over 8kΩ condenser which capacity is above 2000 pF must be connected to suppress the voltage changes of the analog input terminal 3 During conversion do not change the output level of the terminal from H to L or from L to H and not turn on and off the peripheral...

Page 154: ... resolution 1024 steps V 1 H scan line resolution 1024 steps H 1 dot resolution 1024 steps V 1 H scan line resolution 1024 steps Character or tile size 5 16 character sizes line by line basis H 1x 2x 3x 4x V 1x 2x 4x 6x 16 character sizes line by line basis H 1x 2x 3x 4x V 1x 2x 4x 6x Display functions Shutter effect Outlining Shadowing foreground and background Blinking In closed caption mode Ita...

Page 155: ... graphics data 8 Kbytes Data decoder CC GTC Font and tile data read circuit COL CCB HP VP attributes Dot clock Clock sync circuit YM RGB YS OSD registers FRMON HCOUNT Clock divider VCLK2 1 0 GEXTE RAMEND CROMEND GROMEND STC SHP SVP GIHP GIVP CIHP CIVP EONL BFLD Shift register Text graphics and cursor ROM 256 Kbytes Text style and color controller Shutter controller Horizontal position counter Colo...

Page 156: ...ng OSDPOFF to 0 not only disables the OSD display it disables reads from and writes to the OSD registers To operate the OSD set this bit to 1 then set up the OSD registers Using OSDREGE to control read write access to the OSD registers The OSDREGE bit enables or disables read write operations to the OSD reg isters Once you have set the OSD registers you can write a 0 to this bit to disable further...

Page 157: ...l sync signal through the HSYNC pin and the vertical sync signal through the VSYNC pin The pullup resistors and polarity are pro grammable An interrupt must occur so that the microcontroller can detect each VSYNC start field Set the interrupt edge in the IQ1TG 1 0 bits of the EXTMD registers and the OSD input polarity in the VPOL bit of the OSD1 register Note that you must these parameters separat...

Page 158: ...Setup To set up the output pins enable the OSD output pins in the I O registers Select DAC or digital output for RGB and YM Set the YS polarity 7 5 5 Microcontroller Interface The microcontroller writes display data to be sent to the OSD control registers and the VRAM which is assigned to internal RAM space The control registers CRAMEND and GRAMEND hold the end address of the data in the VRAM 7 5 ...

Page 159: ...ay make the CHP and CVP values for the last line smaller than those in the currently displayed line In addition write a 1 to the last line flag of the text layer CLAST 6 Two text lines but no more can overlap on the screen The lower line takes priority appearing to lie on top of the higher line 7 If the horizontal sync signal is asserted while the microcontroller is access ing CHP and CVP that lin...

Page 160: ...he cursor in the cursor layer is programmable to 16W x 16H pixels in standard mode and 32W x 32H pixels in extended mode Select the mode for this layer in the SPEXT bit of the OSD2 register x 007F08 To create a graphic for the cursor layer in extended mode combine four 16 x 16 tiles They are ordered as follows 1 upper left 2 upper right 3 lower left and 4 lower right Set the pointers to these tile...

Page 161: ...6H pixels in standard mode and 16W x 18H pixels in extended mode Select the mode for this layer in the GTHT bit of the OSD2 register x 007F08 You cannot use the tiles created for graphics layer extended mode as cursor tiles In extended mode the tiles are the same size as the characters in the text layer This allows for a cleaner display when text and graphics appear side by side Table 7 4 Associat...

Page 162: ...0 GHP x 04 GLAST 0 GVSZ x 0 GINT 0 GVP x 40 2 97E6 97E4 97E2 97E0 97DE 97DC 97DA 97D8 97D6 4010 4011 4012 4C13 4214 0815 4216 D810 C858 GTC GTC GTC GTC GTC GTC GTC GHP GVP Graphic tile GCB x 0 GPRT 0 GTC x 010 Graphic tile GCB x 0 GPRT 0 GTC x 011 Graphic tile GCB x 0 GPRT 0 GTC x 012 Graphic tile GCB x 3 GPRT 0 GTC x 013 Graphic tile GCB x 0 GPRT 1 GTC x 014 Blank tile GCB x 2 GPRT 0 GTC x 015 Gr...

Page 163: ... 1 2x VP x 3 VSZ 3 6x HSZ 0 1x Repeated tile Line 2 HP x 4 VP x 58 VP x 40 VSZ 0 1x GTC x 000 Palette 1 GTC x 055 Palette 2 Blank GTC x 100 Palette 1 HP x 22 010 Palette 1 011 Palette 1 012 Palette 1 013 Palette 1 013 Palette 1 HSZ 3 4x Display end Line 3 HP x 10 VSZ 1 2x GTC x 181 Palette 1 GTC x 182 Palette 2 013 Palette 1 013 Palette 1 014 Palette 2 Blank Blank Blank 016 Palette 2 ...

Page 164: ...COL x 9 Character code x 006 Character code x 007 Repeat character code CCB x 2 BSHAD 3 CSHAD 0 FRAME 1 BCOL x 7 CCOL x 8 Character code x 008 Blank CCB x 2 Character code x 010 CHSZ x 3 CSHT 0 CHP x 10 CLAST 0 CVSZ x 1 CINT 0 CVP x 70 3 9F5E 9F5C 9F5A 9F58 0300 0310 C044 E030 CC CC CHP CVP Character code x 300 Character code x 310 CHSZ x 0 CSHT 0 CHP x 44 CLAST 1 CVSZ x 0 CINT 0 CVP x 30 Notes 1 ...

Page 165: ...utline Background col 5 Text color A CC x 002 No shadow Outline Background col 5 Text color A HP x 20 CC 006 Box shad 1 Char shad Back col 6 Text col 9 CC 007 Box shad 1 Char shad Back col 6 Text col 9 CC 007 Box shad 1 Char shad Back col 6 Text col 9 CC 007 Same as left CC 007 Same as left CC 007 Same as left CC 008 Box shad 2 Outline Back col 7 Text col 8 HSZ 3 4x Display end Line 3 HP x 10 VSZ ...

Page 166: ... ITALIC FRAME BLINK BCOL3 BCOL2 BCOL1 BCOL0 CCOL3 CCOL2 CCOL1 CCOL0 ID code Underline Italics Outline Blink Background color 16 colors Character color 16 colors CCB Repeat character blank code 0 1 CCBF CCB3 CCB2 CCB1 CCB0 ID code Blank char Number of blank char repetitions CHP Character H position control 1 1 CHSZ1 CHSZ0 CSHT CHP9 CHP8 CHP7 CHP6 CHP5 CHP4 CHP3 CHP2 CHP1 CHP0 ID code H size Shutter...

Page 167: ...E Specifies character outlining black 0 Disable 1 Enable BLINK Specifies character blinking 0 Disable 1 Enable BCOL 3 0 Specifies the background color 1 of 16 colors CCOL 3 0 Specifies the foreground character color 1 of 16 colors CCB Repeat Blank Character Code ID Code 01 CCBF Repeat blank repeat character select 0 Repeat blank 1 Repeat character CCB 3 0 Specifies the number of times up to 16 a b...

Page 168: ...ne 1024 steps are available CVP Character Vertical Position Control Code ID Code 11 CLAST Specifies the last line in the internal RAM text layer This resets the line pointer for character reads from the internal RAM to the first line 0 Disable 1 Enable In closed caption mode only the b 00 b 01 and b 11 settings are available for CVSZ 1 0 The b 10 setting is reserved CVSZ 1 0 Specifies the V size o...

Page 169: ... next line Setting this bit to 1 disables the shuttering function You can disable and enable shuttering on a line by line basis 0 Enable 1 Disable GHP 9 0 Specifies a VCLK indicating the horizontal start position for the next line 1024 steps are available GVP Graphics Vertical Position Control Code ID Code 11 GLAST Specifies the last line in the internal RAM graphics layer This resets the line poi...

Page 170: ...ed area Unused area Code 30 Code 29 Code 2 Code 1 2 bytes Low order 8 bits of graphics code High order 8 bits of graphics code GRAMEND 40 N 5 GRAMEND 40 N 1 GRAMEND 40 n 5 GRAMEND 40 n 1 GRAMEND 7B GRAMEND 40 GRAMEND 3B GRAMEND Line N data Line n data Line 2 data Line 1 data 64 bytes Graphics RAM Addresses When GEXTE 1 CRAMEND 4F CRAMEND 4E CRAMEND 4D CRAMEND 4C CRAMEND 4B CRAMEND 4A CRAMEND 3 CRA...

Page 171: ...hics code High order 8 bits of graphics code GRAMEND 40 N 5 GRAMEND 40 N 1 GRAMEND 40 n 5 GRAMEND 40 n 1 GRAMEND 7B GRAMEND 40 GRAMEND 3B GRAMEND Line N data Line n data Line 2 data Line 1 data 64 bytes GRAMEND 27 GRAMEND 26 GRAMEND 25 GRAMEND 24 GRAMEND 23 GRAMEND 22 GRAMEND 5 GRAMEND 4 GRAMEND 3 GRAMEND 2 GRAMEND 1 GRAMEND Code 20 Code 19 Code 18 Code 3 Code 2 Code 1 2 bytes Low order 8 bits of ...

Page 172: ... the time of A see figure below and the data in the buffer are overwritten to the display data of the first line of line M 1 as time goes by At the time of B the buffer holds n display data of the first line of line M 1 In case n is smaller than N N n display data are needed to display the first line of line M 1 and to be written to the buffer before it is shown on the display Especially when n is...

Page 173: ... character requires 36 bytes GROMEND 7F GROMEND 78 GROMEND 77 GROMEND 70 GROMEND 6F GROMEND 68 GROMEND 67 GROMEND 10 GROMEND 0F GROMEND 08 GROMEND 07 GROMEND Line 1 data Line 2 data Line 3 data Line 15 data Line 16 data 8 bytes GROMEND 80 N 1 1 GROMEND 80 N GROMEND 80 n 1 1 GROMEND 80 n GROMEND FF GROMEND 80 GROMEND 7F GROMEND Code N graphics data Code n graphics data Code 01 graphics data Code 00...

Page 174: ... Setup Example for a Single Line Line 1 data Line 2 data Line 3 data Line 15 data Line 16 data 8 bytes GROMEND 7 GROMEND 6 GROMEND 5 GROMEND 4 GROMEND 3 GROMEND 2 GROMEND 1 GROMEND Sheet 1 bits 7 to 0 Sheet 1 bits 15 to 8 Sheet 2 bits 7 to 0 Sheet 2 bits 15 to 8 Sheet 3 bits 7 to 0 Sheet 3 bits 15 to 8 Sheet 4 bits 7 to 0 Sheet 4 bits 15 to 8 1 byte Graphics tile Sheet 4 Sheet 3 Sheet 2 1 dot 4 bi...

Page 175: ... ROMEND 140 ROMEND 120 ROMEND 100 ROMEND E0 ROMEND C0 ROMEND A0 ROMEND 80 ROMEND 60 ROMEND 40 ROMEND 20 ROMEND Required bytes per tile 2 colors N 4 1 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 32 bytes See fig 7 15 128 bytes Graphic Tile Codes 8 colors N 4 3 1 04 03 02 01 00 96 bytes See fig 7 13 4 colors N 2 1 06 05 04 03 02 01 00 64 bytes See fig 7 14 16 colors N 1 03 02 01 00 128 bytes See fig 7 12...

Page 176: ... ROMEND 168 ROMEND 144 ROMEND 120 ROMEND FC ROMEND D8 ROMEND B4 ROMEND 90 ROMEND 6C ROMEND 48 ROMEND 24 ROMEND Required bytes per tile 2 colors N 4 1 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 36 bytes See fig 7 19 144 bytes Graphic Tile Codes 8 colors N 4 3 1 04 03 02 01 00 108 bytes See fig 7 17 4 colors N 2 1 06 05 04 03 02 01 00 72 bytes See fig 7 18 16 colors N 1 03 02 01 00 144 bytes See fig 7 1...

Page 177: ...END 4D ROMEND 1C ROMEND 1B ROMEND 06 ROMEND 05 ROMEND Line 1 data Line 2 data Line 3 data Line 15 data Line 16 data 6 bytes ROMEND 5 ROMEND 4 ROMEND 3 ROMEND 2 ROMEND 1 ROMEND Sheet 1 bits 7 to 0 Sheet 1 bits 15 to 8 Sheet 2 bits 7 to 0 Sheet 2 bits 15 to 8 Sheet 3 bits 7 to 0 Sheet 3 bits 15 to 8 1 byte Graphics tile 8 color mode Sheet 3 Sheet 2 Sheet 1 1 dot 3 bits 8 colors Bit 15 Bit 0 16 bits ...

Page 178: ...ROMEND 5F ROMEND 5A ROMEND 59 ROMEND 1C ROMEND 1B ROMEND 06 ROMEND 05 ROMEND Line 1 data Line 2 data Line 3 data Line 17 data Line 18 data 6 bytes ROMEND 5 ROMEND 4 ROMEND 3 ROMEND 2 ROMEND 1 ROMEND Sheet 1 bits 7 to 0 Sheet 1 bits 15 to 8 Sheet 2 bits 7 to 0 Sheet 2 bits 15 to 8 Sheet 3 bits 7 to 0 Sheet 3 bits 15 to 8 1 byte Graphics tile 8 color mode 1 dot 3 bits 8 colors Bit 15 Bit 0 16 bits L...

Page 179: ...s corresponding to the tile data stored in the ROM To set up the graphics display colors Write to the fields described below GCOL 1 0 x 007F08 bits 9 and 8 sets the number of colors 2 4 8 or 16 GTC 8 0 GTC bits 8 to 0 in the RAM data specifies the code of the tile to be displayed GPRT GTC bit 9 in the RAM data selects tile color palette 1 or 2 GPT1n x 007FC0 x 007FDE or GPT2n x 007FE0 x 007FFE spe...

Page 180: ...ion mode 00 and 01 No box shadowing 10 Upper left white and lower right black shadows 11 Upper left black and lower right white shadows CPT0 CPTF x 007F80 x 007F9E specifies the colors available for text foreground and background colors FRAME x 007FA2 specifies the color for outlining or character shadowing BBSHD x 007FA4 specifies the black color for box shadowing WBSHD x 007FA6 specifies the whi...

Page 181: ...as specified The PRYM bit allows you to make specific regions of the OSD display trans lucent This bit is disabled when the YSPLT bit is 1 PRYM x 007F08 bit 12 0 Output YS high on all OSD display areas 1 Output YS low on OSD display areas that do not have low YM output YS palette output The YSPLT bit allows you to control the YS output See figure 7 22 YSPLT x 007F06 bit 3 0 Output YS to entire dis...

Page 182: ...r palette 0 output low 0 0 1 0 Color palette F output low Color palette F output low Color palette F output low 0 0 1 1 0 1 0 0 Color palettes 0 and F output low Color palettes 0 and F output low Color palettes 0 and F output low when YM low 0 1 0 1 Color palette 0 output low Color palette 0 output low Color palettes 0 output low when YM low 0 1 1 0 Color palette F output low Color palette F outpu...

Page 183: ...or palette 1 YM3 1 YM2 0 YM1 0 YM0 1 Color palette 0 YM3 0 YM2 0 YM1 0 YM0 1 Color palette 2 YM3 0 YM2 0 YM1 0 YM0 0 Color palette F YM3 1 YM2 0 YM1 0 YM0 1 RGB YS YM 2 F 0 1 1 0 Signal specified in color palette 0 is output RGB YS YM RGB YS YM RGB YS YM RGB YS YM RGB YS YM 2 F 0 1 1 0 RGB YS YM 2 F 0 1 1 0 RGB YS YM RGB YS YM 2 F 0 1 1 0 RGB YM and YS signals are displayed at this line ...

Page 184: ... Switches YM3 Bit 15 R1 1 R2 2 R3 3 G0 4 G1 5 G2 6 G3 7 B0 8 B1 9 B2 10 B3 11 YM0 12 YM1 13 YM2 14 R0 0 InternalDAC R G B YM R G B YM Analog output 4 4 Output YSto entire OS D display area except transparent and semitransparent area s RGBCNT x 007F06 bit 1 RGB CNT RGB CNT YSPL T x 007F06 bit 3 YCNT x 007F06 bit 0 R G B YM YS To pins Color palette Digital input 4 4 ...

Page 185: ... outlining As shown in the figure if a character contains dots in the left or right borders of its field the outlining for those dots appear in the adjacent character field Character shadowing In normal mode writing a 1 to bit 10 CSHAD of the COL setting in the VRAM causes a drop shadow to appear behind all characters following that COL You can specify the color of the shadow in the FRAME register...

Page 186: ...t sides of the box and the color specified in the BBSHD register x 007FA4 appears on the bottom and right sides of the box These positions are reversed if BSHAD0 is 1 Figure 7 25 shows an example of box shadowing As shown in the figure the right hand border of the shadow box appears in the character field to the right of the shadowed text To output a box shadow to the right output a space to the r...

Page 187: ... In both normal and closed caption modes writing a 1 to bit 8 BLINK of the COL setting in the VRAM causes all characters following that COL to blink To use this function you must enable blinking by writing a 1 to bit 5 BLINK of the OSD3 register x 007F0A In closed caption mode you can specify whether or not the underlines blink on underlined blinking characters Set bit 0 UNDF of the OSD3 register ...

Page 188: ...Display Sizes Graphic tile sizes The settings shown are for interlaced displays In progressive displays the vertical size settings GVSZ 1 0 are as follows 01 1x 10 2x and 11 3x The 00 setting is reserved Figure 7 27 Graphic Tile Size Combinations b 00 b 01 b 10 b 11 b 00 b 01 b 10 b 11 1 2 3 4 1 2 6 4 GVSZ 1 0 GHSZ 1 0 16 32 48 64 16 32 64 96 ...

Page 189: ...lays In progressive displays the vertical size settings CVSZ 1 0 are as follows 01 1x 10 2x and 11 3x The 00 setting is reserved In addition in closed caption mode only the b 00 b 01 and b 11 settings are available for CVSZ 1 0 The b 10 setting is reserved Figure 7 28 Character Size Combinations b 00 b 01 b 10 b 11 b 00 b 01 b 10 b 11 1 2 3 4 1 2 6 4 CVSZ 1 0 CHSZ 1 0 16 32 48 64 18 36 72 108 ...

Page 190: ...the CHP 9 0 field of the text display RAM data for the preceding line Valid ranges x 0C CHP HPmax and x 0C CIHP HPmax To set up HPmax equations write HPmax Thsync Thw 0 8 µs Tdot Nchar 16 Hsz or HPmax 1024 Nchar 16 Hsz When setting up the horizontal position you must allow at least 0 8 µs between the end of a line and the leading edge of HSYNC or the display will flicker Thsync is the HSYNC cycle ...

Page 191: ...0 no of H scan lines GIVP GVP x 03 Text Write the vertical position of the first line in the display to the CIVP 9 0 field x 007F1C Write the position of the second and all following lines in the CVP 9 0 field of the text display RAM data for the preceding line Valid ranges x 3F0 no of H scan lines CIVP CVP x 03 VP range calculation example The base graphics line height is 16 dots or H scan lines ...

Page 192: ...clock cycles 12TS after the leading edge of the HSYNC pulse The DMA transfer takes 4TS for each display data word In line 1 or when a graphics and text line begin simultaneously the data transfer requests for both layers occur simultaneously The text data transfer always takes priority The graphics data transfer begins 5TS after the text data transfer ends If a DMA transfer occurs at the same time...

Page 193: ...0 DMA and Interrupt Timing for the OSD Text DMA Text interrupt Graphics interrupt 12Ts 4nTs 5Ts 4nTs Scan line 1 Television Screen Graphics DMA Graphics interrupt Line G1 Graphics DMA Text DMA Text interrupt Line C1 Graphic display Text display Text display Text display Text display Line C2 Horizontal sync pulse Line G2 Graphic display Graphic display ...

Page 194: ...se If your design uses the OSDX clock set the XIO bit x 007F06 bit 7 for the appropriate frequency XIO 0 Less than 20 MHz 1 Greater than 20 MHz Selecting the divide by ratio There are five divide by settings available for any of the clocks described above Table 7 11 shows the register settings for each ratio Table 7 10 OSD Dot Clock Source Settings OSCSEL1 x 007F06 bit 9 OSCSEL0 x 007F06 bit 8 Osc...

Page 195: ... VST1 The top edge of the television screen is x 000 Each integer higher brings the shutter position down one H scan line Determining the horizontal shutter positions HST0 and HST1 The left edge of the television screen is x 000 Each integer higher brings the shutter position right one pixel One pixel or one dot is the smallest display unit in the OSD Table 7 12 Bit Settings for Controlling the Sh...

Page 196: ...ow VSP1 1 V shutter 1 shutters above HSP0 0 H shutter 0 shutters to the right HSP1 1 H shutter 1 shutters to the left SHTRAD 1 All shutters ORed VSON0 VSON1 1 V shutters 0 and 1 on HSON0 HSON1 1 H shutters 0 and 1 on VSP0 1 V shutter 0 shutters above VSP1 0 V shutter 1 shutters below HSP0 1 H shutter 0 shutters to the left HSP1 0 H shutter 1 shutters to the right SHTRAD 1 All shutters ORed HSHT0 V...

Page 197: ...T1 within the following ranges if you are only moving the horizontal shutter The shutter cannot move if you do x 000 to x 003 and x 3FC to x 3FF You can set these values if you wish to prevent horizontal shutter movement Note that the horizontal shutter position does not affect vertical movement Table 7 13 Bit Settings for Controlling Shutter Movement Function VShutter0 Bit Name VShutter1 Bit Name...

Page 198: ...T1 VSHT0 Shuttered region HSHT0 HSHT1 This example shows V shutter 0 moving downward It shutters both the text and the background color in the text layer HSHT0 VSHT1 VSHT0 HSHT1 VSON0 VSON1 1 V shutters 0 and 1 on HSON0 HSON1 1 H shutters 0 and 1 on VSP0 1 V shutter 0 shutters above VSP1 0 V shutter 1 shutters below HSP0 1 H shutter 0 shutters to the left HSP1 0 H shutter 1 shutters to the right S...

Page 199: ...ies to overlap any italicized portion of a closed caption display This distorts the italicized characters Text Set the text shutter control bit CCSHT of the shutter control register SHTC x 007F28 to 1 Text background Set the text background shutter control bit BCSHT of SHTC to 1 Graphics Set the text background shutter control bit GSHT of SHTC to 1 Figure 7 33 shows three setup examples of text la...

Page 200: ...To output blanking to a display that uses a color background enable the color background shutter COLBSHT 1 so that the color background will also be blanked in the shuttered area Figure 7 34 shows two setup examples Figure 7 33 Text Layer Shuttering Setup Examples Television screen CCSHT 0 Shuttering of text foreground disabled BCSHT 0 Shuttering of text background disabled VSHT1 VSHT0 Shuttered r...

Page 201: ... register x 007F16 and or the CISHT bit of the CIHP register x 007F14 to 1 Figure 7 35 shows a setup example for the text layer Figure 7 34 Shutter Blanking Setup Examples Television screen CCSHT 0 Shuttering of text disabled BCSHT 0 Shuttering of text background disabled SHTBLK 1 Shuttered area is blank VSHT1 VSHT0 Shuttered area HSHT0 HSHT1 ABCDE Television screen CCSHT 0 Shuttering of text disa...

Page 202: ... EOMON to 1 as the display start field Table 7 15 shows the criteria that the comparator uses By reading the FRMON bit of EVOD the OSD can determine which register the 4 MSBs will load to on the next VSYNC input To ensure that the display starts at the right field you must also set the EOSEL bit of EVOD so that EOMON becomes 1 at the display start field Figure 7 36 Field Detection Circuit Block Di...

Page 203: ...line EOSEL x 007F0E bit 10 Complement the value EOSEL has for field 1 in a normal display Scrolling in the closed caption mode To implement text layer scrolling in the closed caption mode the program must constantly switch the text display fields This can cause the text lines to display incorrectly To prevent this set the following bits to fix the text lines to the even or odd field characters whi...

Page 204: ...ter x 007F04 GRAMENDA 11 4 holds the programmable portion of the graphics RAM end address and CRAMENDA 11 4 holds the programmable portion of the text RAM end address The low order 4 bits of the address are always x F and the high order 4 bits are always x 9 The available address range Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 205: ...PRT2 Cursor 2 color palette select 0 Graphics color palette 1 1 Graphics color palette 2 STC2 8 0 Cursor 2 Tile Code Use the same ROM data as that used for the graphics Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPRT0 STC08 STC07 STC06 STC05 STC04 STC03 STC02 STC01 STC00 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R W R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 206: ...T3 STC38 STC37 STC36 STC35 STC34 STC33 STC32 STC30 STC30 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R W R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SHSZ1 SHSZ0 SHP9 SHP8 SHP7 SHP6 SHP5 SHP4 SHP3 SHP2 SHP1 SHP0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R W R W R R W R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SVSZ1...

Page 207: ...phics initial horizontal position CIVP Text Initial Vertical Position Register x 007F1C Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GI VSZ1 GI VSZ0 GIVP9 GIVP8 GIVP7 GIVP6 GIVP5 GIVP4 GIVP3 GIVP2 GIVP1 GIVP0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R W R W R R W R W R W R W R W R W R W R W R W R W Table 7 17 Graphics Vertical Size Settings GIVSZ 1 0 Setting 1 Dot Size Interlaced Displays Prog...

Page 208: ...eld register 4 bit register 2 storing field counter value FREG 13 10 Field register 4 bit register 1 storing field counter value HCOUNT HSYNC count x 007F0C This register holds the HSYNC count which indicates the vertical display position It is cleared to 0 on the leading edge of VSYNC Table 7 18 Text Vertical Size Settings CIVSZ 1 0 Setting 1 Dot Size Interlaced Displays Progressive Displays 00 1...

Page 209: ... P45 P46 and output H level before invoking STOP mode 0 Off 1 On OSCSEL 1 0 Oscillator select 00 OSC clock PLL internal synchronization 01 OSDX clock with LC blocking oscillator 10 OSDX clock external source internal synchronization 11 Reserved XIO OSDX frequency select Frequency range 12 to 48 MHz 0 Less than 20 MHz 1 Greater than 20 MHz HPOL HSYNC input polarity select 0 Active low 1 Active high...

Page 210: ... 0 Make color 0 on all palettes transparent 1 Output color 0 as specified GCOL 1 0 Graphics color mode 00 16 color mode 10 4 color mode 01 8 color mode 11 2 color mode COLB Color background control 0 Don t output color background 1 Output color background You cannot set VCLK 2 0 to 100 don t divide when the OSC clock is selected Only select it when the clock source is 32 MHz or less VCLK 2 0 VCLK ...

Page 211: ...DF Underline blinking control 0 Don t blink 1 Blink CAPM Closed caption mode setting 0 Normal display mode 1 Closed caption mode VSHT0 Vertical Shutter 0 Register x 007F20 VSON0 Vertical shutter 0 on off 0 Off 1 On VSP0 Vertical shutter 0 shuttering direction 0 Shutter below 1 Shutter above VSMP0 Vertical shutter 0 movement direction 0 Top to bottom 1 Bottom to top VSM0 Vertical shutter 0 movement...

Page 212: ... 1 On HSP0 Horizontal shutter 0 shuttering direction 0 Shutter to the right 1 Shutter to the left HSMP0 Horizontal shutter 0 movement direction 0 Left to right 1 Right to left HSM0 Horizontal shutter 0 movement control 0 Don t move 1 Move HST0 9 0 Horizontal shutter 0 position Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VSON 1 VSP1 VSMP 1 VSM1 VST1 9 VST1 8 VST1 7 VST1 6 VST1 5 VST1 4 VST1 3 VST1 2 ...

Page 213: ... Off 1 On COLBSHT Color background shutter control 0 Disable 1 Enable SHTSP 1 0 Shutter speed control 00 Move every VSYNC 10 Move every 3 VSYNCs 01 Move every 2 VSYNCs 11 Move every 4 VSYNCs SHTRAD Shutter mode control 0 AND mode 1 OR mode GSHT Graphics shutter control 0 Disable 1 Enable BCSHT Text background shutter control 0 Disable 1 Enable CCSHT Text shutter control 0 Disable 1 Enable Bit 15 1...

Page 214: ...ster x 007FA2 This register contains the color used for text outlining and shadowing When digital output is selected FRAMEYM0 is output as YM FRAMEB0 as B FRAMEG0 as G and FRAMER0 as R When the YS color palette is selected FRAMEYM3 is output as YS FRAMEYM 3 0 YM color code FRAMEB 3 0 Blue color code FRAMEG 3 0 Green color code FRAMER 3 0 Red color code Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPT...

Page 215: ... registers contain one of two sets of colors used in the graphics layer When digital output is selected GPT1nYM0 is output as YM GPT1nB0 as B GPT1nG0 as G and GPT1nR0 as R When the YS color palette is selected GPT1nYM3 is output as YS GPT1nYM 3 0 YM color code GPT1nB 3 0 Blue color code GPT1nG 3 0 Green color code GPT1nR 3 0 Red color code Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BB SHD YM3 BB SH...

Page 216: ...cted GPT2nYM0 is output as YM GPT2nB0 as B GPT2nG0 as G and GPT2nR0 as R When the YS color palette is selected GPT2nYM3 is output as YS GPT2nYM 3 0 YM color code GPT2nB 3 0 Blue color code GPT2nG 3 0 Green color code GPT2nR 3 0 Red color code Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPT2n YM3 GPT2n YM2 GPT2n YM1 GPT2n YM0 GPT2n B3 GPT2n B2 GPT2n B1 GPT2n B0 GPT2n G3 GPT2n G2 GPT2n G1 GPT2n G0 GPT...

Page 217: ...ion fPWM1 fSYSCLK 23 fPWM3 fSYSCLK 25 fPWM5 fSYSCLK 27 fPWM6 fSYSCLK 28 and fPWM8 fSYSCLK 210 The remote signal is input through the RMIN pin Each time the edge detection circuit detects the active edge of the signal the 6 bit counter resets and the sampling clock TS starts counting TS is formed by dividing PWM3 by the value in the frequency division control register RMTC The clock status register...

Page 218: ...olarity select Noise filter CK Remote input signal RMIN Sampling PWM6 21 3 s PWM8 85 5 s 6 6 2 x 00 2 LSBs RMLD x 007EAC RMIR x 007EA2 Q R S Reset CK CK Short long detection Short Long 6 bit counter overflow Remote signal edge detection Reset RMIS x 007EA0 Q R D CK Q R D CK RMTR x 007EAA RMSR x 007EA8 8 8 bit data receive counter RMCS x 007EA6 Loading of 8 bit received data Counter value 7 6 7 6 5...

Page 219: ... value set in the LD 3 0 field of the RMLD register it processes the data in HEAMA format If the interval is 28 to 35 TS cycles it processes the data in 5 6 bit format 8 3 2 Noise Filter The IR remote signal receiver contains a noise filter to eliminate noise from the remote signal To enable the noise filter set the FILTRE bit of the interrupt control register RMIR to 1 The noise filter samples th...

Page 220: ... resets at the first remote signal edge after each trailer detection This mode is for data containing no leader See figure 8 3 When BCEDGS is 1 the counter resets at the second remote signal edge after each trailer detection By ignoring the leader this mode allows the microcon troller to receive 8 bit data that contains a leader See figure 8 4 Figure 8 3 Reception of 8 Bit Data with No Leader Figu...

Page 221: ...data format Table 8 1 Logic Level Conditions for Data Formats Operating Mode Logic Level Conditions Data 0 Data 1 HEAMA format 6 TS cycles 6 TS cycles 5 6 bit format 12 TS cycles 12 TS cycles Table 8 2 Long and Short Data Identification Operating Mode Long Data Short Data HEAMA format 10 TS cycles 2 TS cycles 5 6 bit format 20 TS cycles 4 TS cycles When the microcontroller detects a data trailer t...

Page 222: ...loads 8 bit received data to the reception data transfer register RMTR 8 3 5 4 Pin Edge Detection An interrupt occurs when the remote signal input pin RMIN is asserted The POLSEL bit of RMIR sets the polarity of RMIN The detection output for all four interrupt vectors is an active high pulse asserted at intervals of 1 fSYSCLK Bits 3 to 0 of the RMIR register control the interrupt vectors individua...

Page 223: ...W See section 3 1 CPU Modes on page 72 In SLOW mode fSYSCLK 2 MHz which affects the frequencies of the PWM3 clock and noise filter sampling PWM6 PWM8 Use the SPSLW bit bit 6 of the RMLD register to change which clocks and noise filter sampling that you use Table 8 4 Differences between SLOW and NORMAL Modes SPSLW RMLD bit 6 Normal Mode fSYSCLK 12 MHz SLOW Mode fSYSCLK 2 MHz Noise filter sampling C...

Page 224: ...e TS cycle is the contents of RMTC 1 so load a value from 1 to 255 for a division ratio from 2 to 256 The microcontroller reads the value in the frequency division counter as a ones complement number each digit is complemented Set the RMTC value so that TS T 2 where T is the pulse width of the remote input signal Table 8 6 shows how to define T for the different formats RMTC is an 8 or 16 bit acce...

Page 225: ...ction on off 0 Automatic detect 1 Fixed MODSEL Operating mode select 0 HEAMA format 1 5 6 bit format FILTRE Noise filter input multiplexer on off 0 Pin level 1 Noise filter POLSEL Input polarity 0 Positive edge triggered 1 Negative edge triggered LEADERE Interrupt enable for leader detection 0 Disable 1 Enable TRAILRE Interrupt enable for trailer detection 0 Disable 1 Enable DAT8E Interrupt enable...

Page 226: ...binary counter reset edge select 0 Reset at 1st edge 1 Reset at 2nd edge FMTMON Format monitor 0 HEAMA format 1 5 6 bit format DOMESD Interrupt request on HEAMA leader detection 0 No request 1 Request M56BITD Interrupt request on 5 6 bit leader detection 0 No request 1 Request TRAILRD Interrupt request on trailer detection 0 No request 1 Request DAT8D Interrupt request on 8 bit reception detection...

Page 227: ...tus Register x 007EA6 RMCS indicates the result of the short long data detection It is a 16 bit access register LONGDF Long data format detection Set to 1 when long data is detected SHORTDF Short data format detection Set to 1 when short data is detected TSCNT 5 0 6 bit counter value RMSR Remote Signal Reception Data Shift Register x 007EA8 RMTR Remote Signal Reception Data Transfer Register x 007...

Page 228: ...igital converter clamping circuit sync separator circuit data slicer controller and sampling circuit Note that this section describes CCD0 but all descriptions apply to CCD1 Table 9 1 provides the pin names for each decoder 9 2 Block Diagram Table 9 1 Pins Used for CCD0 and CCD1 Closed Caption Decoder Pin Name CCD0 CVBS0 VREFHS CLH0 CLL0 CCD1 CVBS1 VREFLS CLH0 CLL0 Figure 9 1 Closed Caption Decode...

Page 229: ...ed and figure 9 4 shows that when only CCD0 is used Figure 9 2 Recommended ADC Configuration Figure 9 3 External Connection with Both CCD0 and CCD1 Unused Figure 9 4 External Connection with Only CCD1 Unused 560 pF 240 Ω A D VREFH VREFL CVBS0 CVBS1 CLL CLH VREFHS VREFLS IN OUT CLK Power Down ADDATA 7 0 A D VREFH VREFL IN OUT CLK Power Down ADDATA 7 0 1 µF 1 µF 1 µF 1 µF Clamping circuit 560 pF 240...

Page 230: ...g VBI control ADC control Clamp control Use two cap tion decoders caption 0 ON PCNT0 bp0 0 ON PCNT0 bp4 1 P3MD bp3 2 1 0 1 1 caption 1 ON PCNT0 bp1 0 ON PCNT0 bp5 1 Use one cap tion decoder caption 0 ON PCNT0 bp0 0 ON PCNT0 bp4 1 P3MD bp3 2 1 1 0 1 no caption 1 OFF PCNT0 bp1 1 OFF PCNT0 bp5 0 No use caption decoder no caption 0 OFF PCNT0 bp0 1 OFF PCNT0 bp4 0 P3MD bp3 2 1 0 0 0 no caption 1 OFF PC...

Page 231: ...urrent Medium Current High Current 1 2 3 4 5 6 10 A Off On Off On Off On 4 A 9 Off On Off On Off Off 1 A 3 Off On Off Off Off Off A 0 Off Off Off Off Off Off 3 A 1 On Off Off Off Off Off 9 A 4 On Off On Off Off Off A 10 On Off On Off On Off Notes 1 A compare level reference level 2 The numbers 1 to 6 correspond to the same number in figure 9 5 Table 9 5 Control Registers for Clamping Circuit Regis...

Page 232: ...tip load pulse generator Minimum sync tip detector SYNCMIN 6 0 Pedestal level detector BPLV 6 0 BPLV 6 0 BPPG BPGATE HP Backporch gate level generator BPPST 8 0 Clamping controller SAFE VBION PCLV 6 0 CVBSSEL HLOCKLV 8 0 BCSEL HLOCK Sync separator pulse generator VSEPSAMP HSEPSAMP VSYNC separator HSYNC separator Field detector Sync detector Composite sync separator FQDIV 3 0 VFQDIV 5 0 PSP 5 0 BSP...

Page 233: ... signal Table 9 6 Control Registers for Sync Separator Circuit Register Page CCDO Address CCD1 Address Description Register for setting the sync separator level SPLV 244 x 007ECA x 007EEA Sync separator level set register Register for controlling the sync separator clock FQSEL 243 x 007EC2 x 007EE2 Frequency select register Registers for controlling the HSYNC separator HSEP1 246 x 007ECE x 007EEE ...

Page 234: ...ng is in units of the sampling clock for the HSYNC separator The results of the field detection are stored in the ODDEVEN bit of FIELD 9 3 4 Data Slicer The data slicer contains the maximum and minimum detection circuits the slice level calculator and the slicer The circuit compares the 8 bit digital values output from the ADC to the slice level which can be calculated by the hardware or set in th...

Page 235: ...I capture start timing control register 1 CRI1E 241 x 007E12 x 007E32 CRI capture stop timing control register 1 MAXMIN 238 x 007E02 x 007E22 CRI interval maximum and minimum register SLICE 238 x 007E04 x 007E24 VBI data slice level register FCCNT 237 x 007E00 x 007E20 VBI decoding format select register Table 9 8 Control Registers for Controller and Sampling Circuit Register Page CCDO Address CCD...

Page 236: ...CRI pulse rises and to generate a data sampling clock 9 3 5 2 Data Capture Control The DATAS and DATAE registers control the data capture timing and the CAPDATA register stores the caption data captured on the sampling clock gen erated through CRI detection The HNUM register controls interrupt timing Figure 9 10 Sampling Clock Timing Determination Figure 9 11 Caption Data Capture Timing 21 HSYNC C...

Page 237: ...ter 2 DATAS x 007E18 x 007E38 R W Data capture start timing control register DATAE x 007E1A x 007E3A R W Data capture stop timing control register STAP x 007E1C x 007E3C R W Sampling start position register software setting FCPNUM x 007E1E x 007E3E R Sampling start position register hardware calculation NFSEL x 007EC0 x 007EE0 R W Noise filter select register FQSEL x 007EC2 x 007EE2 R W Frequency ...

Page 238: ...C count value 11 Reserved SLICESEL Hard soft slice level select 0 Select hardware calculation 1 Select software setting SLICELD 2 0 Slice level load timing select When this field is unused tie it to b 000 000 1H 100 1 field 001 2H 101 2 fields 010 4H 110 4 fields 011 8H 111 8 fields SLPULSEL Polarity select for the CRI cycle transition detection 0 Detect 0 to 1 transitions 1 Detect 1 to 0 transiti...

Page 239: ...data slice level software setting Valid range x 00 to x FF SLHD 7 0 VBI data slice level hardware calculation Valid range x 00 to x FF Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAX7 MAX6 MAX5 MAX4 MAX3 MAX2 MAX1 MAX0 MIN7 MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLSF 7 SLSF 6 SLSF 5 SLSF 4...

Page 240: ...7E08 ACQ1W x 007E28 ACQ1E 4 0 Stop position for ACQ capture 1 Valid range x 00 to x 25 ACQ1S 4 0 Start position for ACQ capture 1 Valid range x 00 to x 25 CAPDATA Caption Data Capture Register x 007E0A CAPDATAW x 007E2A CAPDA 15 0 Caption data This register stores the 16 bit captured caption data Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VBI IRQ 4 VBI IRQ 3 VBI IRQ 2 VBI IRQ 1 VBI IRQ 0 SB FLAG HN...

Page 241: ... 7 0 CRI frequency width 3 This field indicates the width in clock units from the third to the fourth rising edge after the CRI CRI1S CRI Capture Start Timing Control Register 1 x 007E10 CRI1SW x 007E30 CRI1S 10 0 Start position for CRI capture 1 Valid range x 000 to x 7FF Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRI2 FQW7 CRI2 FQW6 CRI2 FQW5 CRI2 FQW4 CRI2 FQW3 CRI2 FQW2 CRI2 FQW1 CRI2 FQW0 CRI1...

Page 242: ...rt position as that for CRI detection set in CRI2S The valid range is x 000 to x 7FF Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRI1E 10 CRI1E 9 CRI1E 8 CRI1E 7 CRI1E 6 CRI1E 5 CRI1E 4 CRI1E 3 CRI1E 2 CRI1E 1 CRI1E 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R W R R R R R R W R W R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRI2S 10 CRI2S 9 CRI2S 8 CRI2S 7 CRI2S 6 CRI2S...

Page 243: ...pass filter 1 1 Low pass filter 2 3 or 4 set in NFSW 1 0 NFSW 1 0 Noise filter switch for composite sync separator 00 Low pass filter 3 01 Low pass filter 4 10 Low pass filter 2 11 Low pass filter 1 The cutoff frequencies for low pass filters 1 to 4 are lower in ascending order so that low pass filter 4 eliminates the highest amount of noise Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA E 10 DATA...

Page 244: ...lamping The valid range is x 000 to x 3FF Note that the HSYNC cycle set in this register is only used for detecting the minimum sync level You must also set the correc tion HSYNC cycle in HSEP1 For the NTSC format the setting for this register is x 02FA calculated as follows A D sampling frequency HSYNC cycle 12 MHz 63 µs x 02FA BPPST Backporch Position Register x 007EC6 BPPSTW x 007EE6 BPPST 8 0 ...

Page 245: ... sync tip clamping you should control clamping so as to make this value 16 dec SPLV Sync Separator Level Set Register x 007ECA SPLVW x 007EEA The sync separator uses the value set in this register to separate the com posite sync signal from the composite video signal Figure 9 13 Backporch Position Setting Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BPLV6 BPLV5 BPLV4 BPLV3 BPLV2 BPLV1 BPLV0 SYNC MIN6...

Page 246: ...destal clamping in this field The valid range is x 00 to x 7F VBION VBI setting 0 VBI off 1 VBI on SAFE Clamping current source select This bit is the capacity switch for 5 and 6 in figure 9 5 on page 229 0 High current source 5 and 6 capacity high 1 Medium current source 5 and 6 capacity low CLMODE 1 0 Clamping mode setting 00 Automatic switching depends on the cycle state 01 Sync tip clamping on...

Page 247: ...HLOCKLV 8 0 Sync separator detection threshold This value is compared to the count of the corrected HSYNC The valid range is x 000 to x 1FF and the recommended setting is x 0008 HLOCKLV HSYNC count asynchronous HLOCKLV HSYNC count synchronous Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HS FREQ 10 HS FREQ 9 HS FREQ 8 HS FREQ 7 HS FREQ 6 HS FREQ 5 HS FREQ 4 HS FREQ 3 HS FREQ 2 HS FREQ 1 HS FREQ 0 Rese...

Page 248: ...27H VSYNC separation mask 1 No mask VSEPLMT 2 0 VSYNC separation detection threshold HVCOND Sync Separator Status Register x 007EDA HVCONDW x 007EFA Use this register to monitor the status of the sync separator STPN Status of clamping control pulse signal during STOP COMPSY Composite sync signal status VSEP VSYNC signal status HSEP HSYNC signal status HLOCK Sync detection 0 Asynchronous 1 Synchron...

Page 249: ...007E4C SBFNUMW x 007E6C SBFNUM 10 0 Detected position of start bit flag detected by the hardware TESTA Test Register x 007E4E TESTA x 007E6E SLICE 7 0 Slicing value either from hardware calculation or software setting DATAG Data window for capturing the caption data CRI2G CRI window 2 for detecting the sampling cycle position CRI1G CRI window 1 for calculating the maximum and minimum values ACQG A...

Page 250: ... for the asso ciated ports P15 P17 and P20 P23 see table 10 1 or connect external pullup resistors to these ports The microcontroller writes the pulsewidth modulated data for a PWM block to its associated 8 bit data register PWMn The data register settings determine how long the waveform stays low With a 4 MHz oscillator the PWM output pulse width has a resolution of 1 33 µs 1 fPWM and a cycle of ...

Page 251: ...M0 to PWM6 hold the 8 bit pulsewidth modulated data to be written to the PWMs The registers reset to 0 and they set to 1 when PWM output is high PWM0 PWM6 PWMn Data Registers x 007E70 x 007E7C Note With a 4 MHz oscillator fPWM fSYSCLK 16 Output pulse cycle 28 fPWM 341 3 µs Minimum pulse width 1 fPWM 1 33 µs tLOW PWMn 1 0 67 µs Figure 10 2 PWM Block Diagram Bit 7 6 5 4 3 2 1 0 PWMn7 PWMn6 PWMn5 PWM...

Page 252: ... that form general purpose I O ports Ports 0 1 2 3 4 and 5 are 8 bit ports and port 6 is a 2 bit port All of these pins have alternate functions Ports 7 and 8 are only available with the quad flat package Table 11 1 I O Port Pins Port Associated Pins Port 0 P07 P00 Port 1 P17 P10 Port 2 P27 P20 Port 3 P37 P30 Port 4 P47 P40 Port 5 P57 P50 Port 6 P61 P60 Port 7 P77 P70 Port 8 P87 P80 ...

Page 253: ...H75K F75K 85K F85K LSI User Manual 252 Panasonic 11 2 I O Port Circuit Diagrams Figure 11 1 P00 RMIN IRQ0 Port 0 P0PUP0 0 Pullup off 1 Pullup on P0MD0 0 P00 IRQ0 1 RMIN IRQ0 P0DIR0 0 Port input 1 Port output P0OUT0 Pin P0IN0 RMIN Schmidt trigger 0 Port low output 1 Port high output IRQ0 ...

Page 254: ...nductor Development Company 253 Panasonic Figure 11 2 P03 ADIN0 to P07 ADIN4 Port 0 P0PUPn 0 Pullup off 1 Pullup on P0MDn 0 P03 P04 P05 P06 P07 1 ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 P0DIRn 0 Port input 1 Port output P0OUTn Pin P0INn 0 Port low output 1 Port high output ...

Page 255: ...Manual 254 Panasonic Figure 11 3 P10 ADIN5 IRQ1 P11 ADIN6 IRQ2 and P12 ADIN7 IRQ3 Port 1 P1PUPn 0 Pullup off 1 Pullup on P1MD 2n 0 P10 IRQ1 P11 IRQ2 P12 IRQ3 1 ADIN5 ADIN6 ADIN7 P1DIRn 0 Port input 1 Port output P1OUTn Pin P1INn 0 Port low output 1 Port high output IRQ1 IRQ2 IRQ3 ADIN5 ADIN6 ADIN7 Schmidt trigger ...

Page 256: ...ductor Development Company 255 Panasonic Figure 11 4 P13 ADIN8 WDOUT and P14 ADIN9 STOP Port 1 0 Pullup off 1 Pullup on P1MD 2n 1 P1PUPn P1DIRn 0 Port input 1 Port output P1OUTn Pin 0 Port low output 1 Port high output P1INn ADIN8 ADIN9 P1MD 2n 00 P13 P14 01 WDOUT STOP 10 ADIN8 ADIN9 WDOUT STOP ...

Page 257: ...85K F85K LSI User Manual 256 Panasonic Figure 11 5 P15 ADIN10 PWM0 and P16 ADIN11 PWM1 Port 1 P1PUPn 0 Pullup off 1 Pullup on P1MD 2n 1 00 P15 P16 01 PWM0 PWM1 10 ADIN10 ADIN11 PWM0 PWM1 P1DIRn 0 Port input 1 Port output Pin P1INn P1OUTn 0 Port low output 1 Port high output P1MD 2n ADIN10 ADIN11 ...

Page 258: ...igure 11 6 PWM2 Port 1 P20 PWM3 P21 PWM4 P22 PWM5 and P23 PWM6 Port 2 P1PUPn P2PUPn 0 Pullup off 1 Pullup on P1MD 2n P2MD 2n 0 P17 P20 P21 P22 P23 1 PWM2 PWM3 PWM4 PWM5 PWM6 Low output P1DIRn P2DIRn 0 Port input 1 Port output P1OUTn P2OUTn Pin P1INn P2INn 0 Port low output 1 Port high output M 0 1 U X M 0 1 U X PWM2 PWM3 PWM4 PWM5 PWM6 ...

Page 259: ...asonic Figure 11 7 P24 TM4IC SBT1 Port 2 P2PUP4 0 Pullup off 1 Pullup on 00 P24 01 SBT1 10 TM4IC TM4IC input SBT1 input P2MD9 P2DIR4 0 Port input 1 Port output P2OUT4 Pin P2IN4 0 Port low output 1 Port high output Schmidt trigger ODASCI1 0 Push pull 1 Open drain I2C mode SBT1 output P2MD8 To use as SBT1 set P2MD8 and P2MD9 to 0 ...

Page 260: ... Manual Panasonic Semiconductor Development Company 259 Panasonic Figure 11 8 P27 TM0IO Port 2 P2PUP7 0 Pullup off 1 Pullup on P2MD14 0 P27 1 TM0IO P2DIR7 0 Port input 1 Port output P2OUT7 Pin P2IN7 0 Port low output 1 Port high output M 0 1 U X TM0IO input TM0IO output ...

Page 261: ...OUT B Port 3 and P40 DAYMOUT YM Port 4 P3PUPn P4PUPn 0 Pullup off 1 Pullup on 0 DAC output 1 Digital output P3MDn P4MDn 0 P35 P36 P37 P40 1 DAROUT R DAGOUT G DABOUT B DAYMOUT YM ROUT GOUT BOUT YMOUT Digital output DAROUT DAGOUT DABOUT DAYMOUT DAC output OSD1 bp0 P3DIRn P4DIRn 0 Port input 1 Port output P3OUTn P4OUTn Pin P3INn P4INn 0 Port low output 1 Port high output M 0 1 U X ...

Page 262: ... PCNT0 bit 11 P2OUT5 P2IN5 P2IN6 SBO1 SBI1 0 Port low output 1 Port high output Pin M 00 10 01 U X M U X M U X Schmidt trigger P25 SBI1 SBD1 TM4IOB Pin P26 SBO1 TM4IOA P2PUP6 0 Pullup off 1 Pullup on P2MD13 P2DIR6 0 Port low output 1 Port high output P2OUT6 Schmidt trigger P2MD10 10 TM4IOB 11 Reserved M 00 10 U X SIFSEL1 01 TM4IOB output PCNT0 bit 13 ODASCI1 0 Push pull 1 Open drain For I2C mode P...

Page 263: ...t 1 Port output 0 Push pull 1 Open drain For I2C mode PCNT0 bit 12 ODASCI0 P5OUT5 P5IN5 P5IN6 SBI0 0 Port low output 1 Port high output Pin 0 1 M U X 1 M U X 1 0 M U X Schmidt trigger P55 SBO0 Pin P56 SBI0 SBD0 P5PUP6 0 Pullup off 1 Pullup on 0 P56 1 SBI0 SBD0 P5MD6 0 3 line SBI0 SBO0 SBT0 1 2 line SBD0 SBT0 0 Port input 1 Port output P5DIR6 0 P5OUT6 0 Port low output 1 Port high output Schmidt tr...

Page 264: ... Development Company 263 Panasonic Figure 11 12 P57 SBT0 Port 5 P5PUP7 0 Pullup off 1 Pullup on 0 P57 1 SBT0 P5OUT7 P5IN7 SBT0 input 0 Port low outut 1 Port high output Pin P5MD7 P5DIR7 0 Port input 1 Port output 0 Push pull 1 Open drain For I2 C mode PCNT0 bit 12 ODASCI0 Schmidt trigger SBT0 output ...

Page 265: ...P0PUP2 0 Pullup off 1 Pullup on 0 Pullup off 1 Pullup on P0MD2 0 P02 1 SCL1 P0DIR2 0 Port input 1 Port output P0OUT2 SCL output P0IN2 P6IN1 SCL input 0 Port low output 1 Port high output I2CSEL1 I2CSEL0 Pin M 0 1 U X Schmidt trigger Schmidt trigger P02 SCL1 P6PUP1 P6MD1 0 P61 1 SCL0 P6DIR1 0 Port input 1 Port output P6OUT1 0 Port low output 1 Port high output Pin M 0 1 U X P61 SCL0 ...

Page 266: ...P0PUP1 0 Pullup off 1 Pullup on 0 Pullup off 1 Pullup on P0MD1 0 P01 1 SDA1 P0DIR1 0 Port input 1 Port output P0OUT1 SDA output P0IN1 P6IN0 SDA input 0 Port low output 1 Port high output I2CSEL1 I2CSEL0 M 0 1 U X Schmidt trigger Schmidt trigger Pin P01 SDA1 P6PUP0 P6MD0 0 P60 1 SDA0 P6DIR0 0 Port input 1 Port output P6OUT0 0 Port low output 1 Port high output M 0 1 U X Pin P60 SDA0 ...

Page 267: ...nt Company MN102H75K F75K 85K F85K LSI User Manual 266 Panasonic Figure 11 15 P31 CVBS0 and P32 CVBS1 Port 3 P3PUPn 0 Pullup off 1 Pullup on P3MDn 0 P31 P32 1 CVBS0 CVBS1 CVBS0 CVBS1 P3DIRn 0 Port input 1 Port output P3OUTn Pin P3INn 0 Port low output 1 Port high output ...

Page 268: ...er Manual Panasonic Semiconductor Development Company 267 Panasonic Figure 11 16 P30 CLH and P33 CLL Port 3 P3PUPn 0 Pullup off 1 Pullup on 0 P30 P33 1 CLH CLL CLH CLL P3MD2 P3DIRn 0 Port input 1 Port output P3OUTn Pin P3INn 0 Port low output 1 Port high output P3MD3 ...

Page 269: ...or Development Company MN102H75K F75K 85K F85K LSI User Manual 268 Panasonic Figure 11 17 P34 VREF Port 3 P3PUP4 0 Pullup off 1 Pullup on P3MD4 0 P34 1 VREF VREF P3DIR4 0 Port input 1 Port output P3OUT4 Pin P3IN4 0 Port low output 1 Port high output P34 VREF ...

Page 270: ...4 TM5IC HI1 Port 4 P4PUPn 0 Pullup off 1 Pullup on P4DIRn 0 P41 P42 P43 1 TM1IO TM5IOA TM5IOB P4MDn 0 Port input 1 Port output P4OUTn Pin 0 Port low output 1 Port high output M 0 1 U X P4INn TM1IO input TM5IOA input TM5IOB output HI0 TM1IO output TM5IOA output TM5IOB output P4DIR4 0 Port input 1 Port output P4MD4 0 P44 1 TM5IC HI1 P4OUT4 0 Port low output 1 Port high output TM5IC HI1 input Pin P44...

Page 271: ...P6 0 Cut 1 Connect 0 Pullup off 1 Pullup on LCCNT is the OSDXI O oscillation control signal from the OSD 0 Disable 1 Enable P4MD5 0 P45 P46 1 OSDXI OSDXO P4DIR6 0 Port input 1 Port output P4OUT6 P46 OSDXI Pin P4IN6 0 Port low output 1 Port high output LCCNT To internal circuit P45 OSDXO Pin P4PUP5 0 Pullup off 1 Pullup on P4OUT5 0 P45 1 OSDXI P4DIR5 0 Port input 1 Port output P4IN5 ...

Page 272: ...r Manual Panasonic Semiconductor Development Company 271 Panasonic Figure 11 21 P47 HSYNC Port 4 P4PUP7 0 Pullup off 1 Pullup on P4MD7 0 P47 1 HSYNC P4DIR7 0 Port input 1 Port output P4OUT7 Pin 0 Port low output 1 Port high output P4IN7 Schmidt trigger HSYNC P47 HSYNC ...

Page 273: ...y MN102H75K F75K 85K F85K LSI User Manual 272 Panasonic Figure 11 22 P50 SYSCLK Port 5 P5PUP0 0 Pullup off 1 Pullup on P5MD0 0 P50 1 SYSCLK SYSCLK or divided SYSCLK output P5DIR0 0 Port input 1 Port output P5OUT0 Pin P5IN0 0 Port low output 1 Port high output 0 1 M U X P50 SYSCLK ...

Page 274: ... LSI User Manual Panasonic Semiconductor Development Company 273 Panasonic Figure 11 23 P51 YS Port 5 P5PUP1 0 Pullup off 1 Pullup on P5MD1 0 P51 1 YS YSOUT P5IN1 P5DIR1 0 Port input 1 Port output P5OUT1 Pin 0 Port low output 1 Port high output M 0 1 U X P51 YS ...

Page 275: ...ompany MN102H75K F75K 85K F85K LSI User Manual 274 Panasonic Figure 11 24 P52 IRQ4 VI0 Port 5 P5PUP2 0 Pullup off 1 Pullup on P5MD2 0 P52 1 IRQ4 VI0 P5DIR2 0 Port input 1 Port output P5OUT2 Pin 0 Port low output 1 Port high output P5IN2 Schmidt trigger IRQ4 VI0 P52 IRQ4 VI0 ...

Page 276: ...85K LSI User Manual Panasonic Semiconductor Development Company 275 Panasonic Figure 11 25 P53 RST Port 5 P5PUP3 0 Pullup off 1 Pullup on P5OUT3 0 Port low output 1 Port high output P5DIR3 0 Port input 1 Port output P5IN3 NTGTRST Pin Schmidt trigger P53 RST ...

Page 277: ... MN102H75K F75K 85K F85K LSI User Manual 276 Panasonic Figure 11 26 P54 IRQ5 VSYNC Port 5 P5PUP4 0 Pullup off 1 Pullup on P5MD4 P5DIR4 0 Port input 1 Port output P5OUT4 Pin 0 Port low output 1 Port high output 0 P54 IRQ5 1 IRQ5 VSYNC P5IN4 Schmidt trigger IRQ5 VSYNC P54 IRQ5 VSYNC ...

Page 278: ... P7P8CNT bit of the PCNT2 register forces the pullup resistors on for ports 7 and 8 P7PUP and P8PUP are only valid when P7P8CNT is 1 P0OUT P5OUT Ports 0 5 Output Control Registers x 00FFC0 x 00FFC5 Writing a 0 to P5OUT3 causes a reset to occur P7OUT P8OUT Ports 7 8 Output Control Registers x 00FFC8 x 00FFCA P6OUT Port 6 Output Control Register x 00FFC6 The PnOUT registers contain the port output d...

Page 279: ...FE0 x 00FFE5 P7DIR P8DIR Ports 7 8 I O Control Registers x 00FFE8 x 00FFEA P6DIR Port 6 I O Control Register x 00FFE6 The PnDIR registers control the I O direction of the ports The bit number corresponds to the associated pin number For instance P0DIR7 applies to the P07 pin These are 8 bit access registers 0 Input 1 Output Bit 7 6 5 4 3 2 1 0 PnIN7 PnIN6 PnIN5 PnIN4 PnIN3 PnIN2 PnIN1 PnIN0 Reset ...

Page 280: ...itch 0 P06 1 ADIN3 P0MD5 P05 function switch 0 P05 1 ADIN2 P0MD4 P04 function switch 0 P04 1 ADIN1 P0MD3 P03 function switch 0 P03 1 ADIN0 P0MD2 P02 function switch 0 P02 1 SCL1 P0MD1 P01 function switch 0 P01 1 SDA1 P0MD0 P00 output switch Control the IRQ0 interrupt enable settings in the interrupt control registers 0 P00 RMIN IRQ0 1 RMIN IRQ0 Bit 7 6 5 4 3 2 1 0 P0MD7 P0MD6 P0MD5 P0MD4 P0MD3 P0M...

Page 281: ...erved P1MD 9 8 P14 output and function switch 00 P14 01 ADIN9 10 STOP 11 Reserved P1MD 7 6 P13 output switch 00 P13 01 ADIN8 10 WDOUT 11 Reserved P1MD4 P12 function switch 0 P12 IRQ3 1 ADIN7 P1MD2 P11 function switch 0 P11 IRQ2 1 ADIN6 P1MD0 P10 function switch Control the IRQ3 IRQ2 and IRQ1 interrupt enable settings in the inter rupt control registers 0 P10 IRQ1 1 ADIN5 Bit 15 14 13 12 11 10 9 8 ...

Page 282: ...n switch If you set this field to b 10 select SBI1 or SBD1 in bit 11 of PCNT0 To use TM4IOB as an output pin set this field to b 01 and set the P2DIR5 bit to 1 00 P25 01 TM4IOB 10 SBI1 or SBD1 11 Reserved P2MD 9 8 P24 output and function switch To use SBT1 as an input set this field to b 00 and set the P2DIR4 bit to 0 00 P24 01 TM4IC 10 SBT1 11 Reserved P2MD6 P23 output switch 0 P23 1 PWM6 P2MD4 P...

Page 283: ... 1 select DAGOUT or G in the RGBC bit of ODS1 0 P36 1 DAGOUT or G P3MD5 P35 output switch If you set this field to 1 select DAROUT or R in the RGBC bit of ODS1 0 P35 1 DAROUT or R P3MD4 P34 function switch 0 P34 1 VREF P3MD 3 1 P33 P30 function switch Set P3MD3 to 1 only when P3MD 2 1 is 01 otherwise set it to 0 000 P30 P31 P32 P33 101 CLH CVBS0 P32 CLL 010 CLH P31 CVBS1 CLL 011 CLH CVBS0 CVBS1 CL...

Page 284: ...ut switch 0 P44 TM5IC HI0 1 TM5IC HI0 P4MD3 P43 output switch To use TM5IOB as an output pin set this bit to 1 and set the P4DIR3 bit to 1 0 P43 HI1 1 TM5IOB HI1 P4MD2 P42 output switch To use TM5IOA as an output pin set this bit to 1 and set the P4DIR2 bit to 1 0 P42 1 TM5IOA P4MD1 P41 output switch To use TM1IO as an output pin set this bit to 1 and set the P4DIR1 bit to 1 0 P41 1 TM1IO P4MD0 P4...

Page 285: ... function switch 0 P54 IRQ5 VSYNC 1 IRQ5 VSYNC P5MD3 This bit exists but contains no function P5MD2 P52 output switch 0 P52 IRQ4 VI0 1 IRQ4 VI0 P5MD1 P51 output switch 0 P51 1 YS P5MD0 P50 output switch If you set this bit to 1 set the SYSCLK frequency in bits 15 14 of PCNT0 0 P50 1 SYSCLK divided SYSCLK output P6MD Port 6 Output Mode Register x 00FFFC P6MD is an 8 bit access register P6MD1 P61 fu...

Page 286: ...e SBI1 SBO1 SBT1 1 Two line enable SBD1 SBT1 SIFSEL0 Serial port 0 interface select 0 Three wire enable SBI0 SBO0 SBT0 1 Two wire enable SBD0 SBT0 I2CSEL1 SDA1 SCL1 enable 0 Disable 1 Enable To use P01 SDA1 and P02 SCL1 as general purpose port pins you must both select the ports in the port mode register and disable this bit I2CSEL0 SDA0 SCL0 enable 0 Disable 1 Enable To use P60 SDA0 and P61 SCL0 ...

Page 287: ...power dissipation The program must write a 1 to this bit before writing any values to the OSD registers 0 Disable 1 Enable PLLPOFF PLL circuit enable 0 Enable 1 Stop ADC1ON ADC circuit enable for closed caption decoder 1 0 Disable 1 Enable ADC0ON ADC circuit enable for closed caption decoder 0 0 Disable 1 Enable HCNTOFF H counter circuit enable 0 Enable 1 Disable RMCOFF IR remote signal receiver c...

Page 288: ...he quad flat package 0 Pull up 1 Don t pull up I2COFF I2C function enable 0 Enable 1 Disable PWMOFF PWM function enable 0 Enable 1 Disable Setting the I2COFF or PWMOFF bits to 1 shuts off the system clock sup ply to the associated block which reduces power dissipation OSDREGE OSD registers read write enable To read or write to the OSD registers you must first set this bit to 1 0 Disable 1 Enable B...

Page 289: ...e the function to send internal status information to an external location This enables system level examination of the internal status even with the mask ROM version To use the ROM correction function embed a routine such as that shown in figure 12 2 in the ROM As figure 12 1 shows the function lies between the microcontroller and ROM blocks First set the correction data for any sixteen non OSD a...

Page 290: ...nsiderations At reset the ROM correction address match and data registers contain all 0s Since a reset also disables ROM correction in ROMCEN the ROM will still operate normally Only read from or write to the address match registers while ROM correction is disabled in ROMCEN Otherwise an error may occur in the match detection circuit Note that the address match and data registers only allow full r...

Page 291: ...ss 2 AMCHIH2 x 00FD0A AMCHIL2 x 00FD08 CHDAT2 x 00FD48 Address 3 AMCHIH3 x 00FD0E AMCHIL3 x 00FD0C CHDAT3 x 00FD4C Address 4 AMCHIH4 x 00FD12 AMCHIL4 x 00FD10 CHDAT4 x 00FD50 Address 5 AMCHIH5 x 00FD16 AMCHIL5 x 00FD14 CHDAT5 x 00FD54 Address 6 AMCHIH6 x 00FD1A AMCHIL6 x 00FD18 CHDAT6 x 00FD58 Address 7 AMCHIH7 x 00FD1E AMCHIL7 x 00FD1C CHDAT7 x 00FD5C Address 8 AMCHIH8 x 00FD22 AMCHIL8 x 00FD20 C...

Page 292: ...ion enable 0 Disable 1 Enable ROMCEN8 Address 8 ROM correction enable 0 Disable 1 Enable ROMCEN7 Address 7 ROM correction enable 0 Disable 1 Enable ROMCEN6 Address 6 ROM correction enable 0 Disable 1 Enable ROMCEN5 Address 5 ROM correction enable 0 Disable 1 Enable ROMCEN4 Address 4 ROM correction enable 0 Disable 1 Enable ROMCEN3 Address 3ROM correction enable 0 Disable 1 Enable ROMCEN2 Address 2...

Page 293: ... Correction data bit D13 or D5 for address n CHD4 Correction data bit D112 or D4 for address n CHD3 Correction data bit D11 or D3 for address n CHD2 Correction data bit D10 or D2 for address n CHD1 Correction data bit D9 or D1 for address n CHD0 Correction data bit D8 or D0 for address n Bit 7 6 5 4 3 2 1 0 CHAD 23 CHAD 22 CHAD 21 CHAD 20 CHAD 19 CHAD 18 CHAD 17 CHAD 16 Reset 0 0 0 0 0 0 0 0 R W R...

Page 294: ...nsfer At that time any device addressed is considered a slave Table 13 1 defines some I2C bus terminology Figure 13 1 Example of I2 C Bus Application Table 13 1 I2C Bus Terminology Term Description Transmitter The device that sends the data to the bus Receiver The device that receives the data from the bus Master The device that initiates a transfer generates clock signals and termi nates a transf...

Page 295: ...ble operating modes for devices on the I2 C bus Figure 13 2 Connection of Two Microcontrollers to the I2 C Bus Table 13 2 Operating Modes for Devices on an I2C Bus Operating Mode Description Master transmitter Device that generates the serial transfer clock SCL signal and transmits serial data to a slave device in sync with SCL Master receiver Device that generates the SCL signal and receives seri...

Page 296: ...pt Interrupt Interrupt Normally ACK 0 MN102H51K Master S Address 7 bits R W Data 8 bits Data 8 bits P Slave ACK ACK ACK R W 1 Interrupt Interrupt Interrupt ACK 1 signals transfer end to slave transmitter MN102H51K Master S Address 7 bits R W Data 8 bits Data 8 bits P Slave ACK ACK ACK R W 1 Interrupt Interrupt Interrupt ACK 1 signals transfer end to slave transmitter Ack 0 Ack 1 When the microcont...

Page 297: ...a transfer to the I2 C bus at any time Figure 13 4 I2 C Bus Controller Block Diagram Table 13 3 Control Registers for Clamping Circuit Register Page Address Description I2CDTRM 304 x 007E40 I2 C transmission data register I2CDREC 305 x 007E42 I2 C reception data register I2CMYAD 305 x 007E44 I2 C self address register I2CCLK 306 x 007E46 I2 C clock control register I2CBRST 306 x 007E48 I2 C bus re...

Page 298: ...forms bus arbitration for a multimaster system When it loses an arbitration the hardware immediately stops the data transfer and generates an interrupt Address decoding The I2 C bus controller decodes the microcontroller s address set in the I2CMYAD register when the microcontroller is a slave device It also decodes the general code address 0 Forced bus reset Through software control by a write to...

Page 299: ...n 1 set bits 1 and 2 of the P0MD register x 00FFF0 Table 13 4 shows the register settings required to use either SDA0 SCL0 or SDA1 SCL1 alone and figure 13 5 shows the control circuit for this pin setup Table 13 4 Registers Settings for SDA0 SCL0 or SDA1 SCL1 Ports Register Bit SDA0 SCL0 Only SDA1 SCL1 Only P0MD x 00FFF0 1 0 selects P01 1 selects SDA1 2 0 selects P02 1 selects SCL1 P6MD x 00FFFC 0...

Page 300: ...tHIGH tBUF tHD STA tLOW tR tSU STO tHD STA tF tSU DAT tSU STA S Sr P Table 13 5 SDA and SCL Waveform Characteristics Parameter Symbol Min Max Unit SCL clock frequency fSCL 0 100 kHz Bus free time between a stop and start condition tBUF 20 µs Hold time repeated start condition tHD STA 4 0 Low period of the SCL clock tLOW 4 7 High period of the SCL clock tHIGH 4 0 Setup time for a repeated start con...

Page 301: ...cting a clock frequency of 80 kHz 2 Set the I2CDTRM register x 007E40 to x 05FD This sets STA to 1 STP to 0 and ACK to 0 Bits 7 to 1 of the transmission data setting x FD indi cate the address b 1111110 of the slave device from which the microcon troller will request the data and bit 0 indicates the read write setting bit 0 1 read 13 6 1 2Setting Up the First Interrupt When an ACK 0 signal returns...

Page 302: ...0 With this setting the microcontroller returns an ACK 1 signal on the ninth clock 13 6 1 4Setting Up the Third Interrupt When the microcontroller receives the data x 33 from the slave device it returns an ACK 1 signal and the I2 C bus controller generates an interrupt At this point implement the following settings To set up the interrupt Set the I2C0ICH and I2C0ICL register pair x 00FC9C to x 010...

Page 303: ...CDTRM register x 007E40 to x 0000 This sets STA STP ACK and the transmission data to 0s With this setting the microcontroller returns an ACK 0 signal when an address match occurs The master sends data the slave address to the slave microcontroller in sync with the master clock When the R W bit 1 the microcontroller changes from a slave receiver to a slave transmitter 13 6 2 2Setting Up the First I...

Page 304: ...e the I2 C bus controller status The previous read from I2CDREC cleared the AAS so AAS should be 0 2 Set the I2CDTRM register x 007E40 to x 01AA0 This sets STA to 0 STP to 0 ACK to 1 and the transmission data to x AA The microcontroller does not need to issue an ACK signal in this transfer so the ACK bit should be 1 3 Begin transmitting data in sync with the clock from the master 13 6 2 4Setting U...

Page 305: ...y byte transfer on the ninth clock pulse ACK is normally 1 and transitions to 0 to output an acknowl edge for instance if the master or slave receiver has received a data byte DT 7 0 Data to be transmitted The parallel data in this field is converted to serial data for transmission to the I2C bus It is shifted out MSB first to the interface Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STA STO ACK DT7...

Page 306: ... address on the bus matches the contents of the address register or matches the general address x 00 AAS resets after a read from the I2CDREC register LAB Lost arbitration bit Set to 1 when the microcontroller loses a bus arbitration LAB resets when I2CDTRM indicates a start condition STA 1 BB Bus busy bit A start condition on the bus sets this flag to 0 and a stop condition resets it to 1 The mic...

Page 307: ...k line low and resetting the I2C bus This function works in all I2C modes After a forced reset the microcontroller is in slave receiver mode This reset does not change the contents of the I2CMYAD and I2CCLK registers 0 Force bus to reset 1 Steady state I2CBSTS I2 C Bus Status Register x 007E4A I2CBSTS is a two bit read only register that monitors the status of the I2 C bus SDAS SDA data line statu...

Page 308: ...gram Note In this example HI0 is active high and VSYNC is active low Figure 14 2 H Counter Operation Example Divider Polarity switch PWM10 waveform M U X VSYNC VI0 10 bit register 10 bit counter HI0 HI1 Data bus 1024 µs 2048 µs 4096 µs 8192 µs Reset Latch Count source Selected in SELR 20 00 SELR 21 01 fields of HCCNT0 HCCNT1 registers Selected in REDG0 REDG1 bits of HCCNT0 HCCNT1 registers Selecte...

Page 309: ... H counter set the port 4 and 5 output control registers P4OUT and P5OUT to 0 and set the H counter pins to input To use HI0 set the P4DIR3 bit x 00FFE4 to 0 To use HI1 set the P4DIR4 bit x 00FFE4 to 0 To use VI0 set the P5DIR2 bit x 00FFE5 to 0 To use VSYNC set the P5DIR4 bit x 00FFE5 to 0 Note In this example HI0 is active high and VSYNC is active low Figure 14 3 H Counter Input Signal Timing Ta...

Page 310: ...ctive edge to active edge input of VSYNC pin If your application uses one of the fixed clocks based on divided PWM output 1024 2048 4098 or 8096 µs you must also set up the PWM circuit See section 10 Pulse Width Modulator on page 249 To use the H counter you must always set the HCNTOFF bit of the PCNT0 register to 0 To use the PWM function always set the PWMOFF bit of the PCNT2 register x 00FF92 t...

Page 311: ...s 011 8192 µs 100 VI0 101 VSYNC All other settings default to 1024 µs HCCNT1 H Counter Control Register 1 x 007EB2 SEDG1 Polarity select for count source signal HI1 0 Active low 1 Active high SEDG1 Polarity select for reset signal 0 Active low 1 Active high SELR 21 01 Reset signal select 000 1024 µs 001 2048 µs 010 4096 µs 011 8192 µs 100 VI0 101 VSYNC All other settings default to 1024 µs Bit 15 ...

Page 312: ...ta Register 1 x 007EB6 HCD 91 01 Count from HI1 source signal This field stores the HI1 clock source count It becomes x 3FF on over flow Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HCD 90 HCD 80 HCD 70 HCD 60 HCD 50 HCD 40 HCD 30 HCD 20 HCD 10 HCD 00 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HCD 91 HCD 81 HCD 71 HCD 61 HCD 51 ...

Page 313: ... HCO UNT0 H counter registers 007EC0 HSEP1 CLAMP SPLV BPLV SYNC MIN BPPST SCMING FQSEL NFSEL Sync separator 1 registers 007ED0 CLPCND 1 HVCOND VCNT HDISTW HLOCKLV FIELD HSEP2 007EE0 HSEP1W CLAMPW SPLVW BPLV W SYNC MINW BPPSTW SCMING W FQSELW NFSELW Sync separator 2 registers 007EF0 CLPCND1W HVCONDW VCNTW HDIS TWW HLOCK LVW FIELDW HSEP2W 007F00 EVOD HCOVNT OSD3 OSD2 OSD1 RAMEND GROMEN D CROMEN D OS...

Page 314: ...CL VBIV ICH VBIV ICL SCR0 ICH SCR0 ICL SCT0 ICH SCT0 ICL AN ICH AN ICL 00FC90 I2C ICH I2C ICL SCR1 ICH SCR1 ICL SCT1 ICH SCT1 ICL OSDC ICH OSDC ICL OSD G ICH OSD G ICL 00FCA0 00FCB0 00FCC0 00FCD0 00FCE0 00FCF0 ROMCTSTH test register ROMCTSTL test register EXTMD ROMCEN ROM correction registers and external interrupt mode register 00FD00 AMC HIH3 AMCHIL3 AMC HIH2 AMCHIL2 AMC HIH1 AMCHIL1 AMC HIH0 AM...

Page 315: ...timer 5 registers 00FEA0 00FEB0 00FEC0 00FED0 00FEE0 00FEF0 00FF00 AN3BUF AN2BUF AN1BUF AN0BUF ANTST test register ANCTR ADC registers 00FF10 AN11BUF AN10BUF AN9BUF AN8BUF AN7BUF AN6BUF AN5BUF AN4BUF 00FF20 00FF30 00FF40 00FF50 00FF60 00FF70 FBEWER FAR EGEX FAREG FDREG FCREG Flash memory write control registers 00FF80 MEMMD1 EXWMD External memory wait control registers 00FF90 PCNT2 PCNT0 I O port ...

Page 316: ...Register Map MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 315 Panasonic ...

Page 317: ... divided into three main areas Load program area 1 kilobyte x 0x80000 to x 0x803FF This area stores the load program for the serial writer It is overwritten in PROM writer mode Fixed user program area 7 kilobytes x 0x80400 to x 0x81FFD This area stores a user program that is write protected in serial programming mode It is overwritten in PROM writer mode User program area 248 kilobytes x 0x82000 t...

Page 318: ...e microcontroller is inserted into a dedicated adaptor socket which connects to DATA I O s LabSite PROM writer When the microcontroller connects to the adaptor socket it auto matically enters PROM writer mode The adaptor socket ties the microcontroller pin states to PROM writer mode and programming occurs without any reference to the microcontroller pin states Figure B 2 PROM Writer Hardware Setup...

Page 319: ... Package external view Installed in 84 pin QFP 64 pin SDIP Adaptor Installed in Ordering information Part no FLS84F18 102HF57 OEM Matsushita Electric Indus trial Co Ltd Ordering information Part no FLS64SD 102HF51 OEM Matsushita Electric Indus trial Co Ltd Third party PROM writer Gang writer Single unit writer Model 1930 OEM Minato Electronics 4105 Minami Yamada cho Tsuzuki ku Yokohama Japan Tel 0...

Page 320: ...on describes the microcon troller hardware system configuration software register map and protocol for this type of programming operation Hardware requirements Onboard serial writer YDC model AF200 provisional Add on circuit for target board Flash programming connectors or pins for target board Software requirements Serial writer load program installed in first kilobyte of MN102HF75K 85K EEPROM Pr...

Page 321: ...ntroller on the target board You must supply an external VDD source to the target board The serial writer supplies the VPP source You must provide the personal computer that holds the IC card To order the serial writer contact Provisional Yokogawa Digital Computer Co Ltd Microcontroller System Joint Headquarters Equipment Business Center Keio Fuchu 1 chome Building 7F 1 9 Fuchu cho Fuchu shi Tokyo...

Page 322: ...board to the RST SBT and SBD pins Use a pullup resistor value of 10 kΩ 10 Install a switch on the target board to toggle between RST for serial programming and RST for normal operation Alternatively install a wired OR connection For a wired OR connection disable RST for normal operation during serial programming RST SBT and SBD are output from the serial writer through an open con nection Figure B...

Page 323: ...ion bit LSB first Maximum clock speed 10 MHz Positive I O logic Two I O pins SBT1 and SBD1 pins with alternate I O port functions B 4 3 2 Serial Writer Interface Block Diagram When programming the memory you need not be aware of these microcontroller hardware connections However it is vital that you take these connections into account when designing your target board so that the serial writer can ...

Page 324: ...holds the password for the serial writer Enter an 8 character ASCII code in this space Reserved area Do not write to this area Branch instruction to reset service routine Normally reset servicing starts at address x 0x80000 but the soft branch instruction in the serial writer load program branches to x 0x82010 This address must hold a JMP instruction pointing to the real start address for the rese...

Page 325: ...t needs to operate the serial writer and program the EEPROM No other memory area can be used for this purpose You do not need to know about RAM allo cation to program the EEPROM Reserved area Do not write to this area B 4 5 Microcontroller Clock on the Target Board For the clock supply to the microcontroller on the target board use the existing target board clock The OSC oscillator clock for the m...

Page 326: ... turn VPP on At this point output RST SBD low 3 Through the serial writer drive the RST pin from time B in figure B 8 when SBT goes high on microcontroller power up for t2 cycles The microcontrol ler initializes 4 Through the serial writer drive the SBD pin low from time C in figure B 8 when RST goes high on microcontroller power up for t3 cycles This tells the microcontroller that it is connected...

Page 327: ... be low and SBT high 2 After the program waits tWAIT1 10 milliseconds SBD must still be low and SBT high 3 Within tWAIT2 100 milliseconds both SBD and SBT must be high If any of these conditions is not met control returns to the user program Figure B 9 Load Program Start Flow SBT pin high SDB pin low Yes No Wait tWAIT1 SBT pin high SDB pin low Yes No Has tWAIT2 passed No SBT pin high SDB pin high ...

Page 328: ...0x82010 B 4 7 2 Branching to the Interrupt Start Routine In the interrupt start address place a simple branch instruction pointing to address x 0x82018 Figure B 10 Flow of Branch to Reset Start Routine Figure B 11 Flow of Branch to Interrupt Start Routine Serial writer Yes No Reset start Start serial writer load program Branch to address x 82010 Execute user program Generate 10 cycle delay Interru...

Page 329: ...data has already set is forbid den As the figure shows the write occurs after the memory is completely erased The erase routine consists of three steps first writing all zeros to the entire memory space next erasing the memory and finally reversing B 6 Programming Times Table B 7 shows the time required for PROM and serial programming and repro gramming erasing and programming Figure B 12 EEPROM P...

Page 330: ...over Pub number C 22385 010E 22385 011E Colophon C September 2001 1st Edition October 2001 1st Edition 1st Printing Sales office C Latest version MN102H75K F75K 85K F85K LSI User s Manual Description Record of Changes Ver 1 0 to 1 1 Definition A add D delete C modify change ...

Page 331: ...N10200 Series Linear Addressing High Speed Version C Compiler User Manual Language Description Describes the syntax for the C compiler MN10200 Series Linear Addressing High Speed Version C Compiler User Manual Library Reference Describes the standard libraries for the C compiler MN10200 Series Linear Addressing High Speed Version Cross Assembler User Manual Describes the assembler syntax and notat...

Page 332: ...13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 NC P71 P10 ADIN5 IRQ1 P11 ADIN6 IRQ2 P12 ADIN7 IRQ3 P72 P13 ADIN8 WDOUT P14 ADIN9 STOP P73 P15 ADIN10 PWM0 P16 ADIN11 PWM1 P17 PWM2 P20 PWM3 P21 PWM4 P22 PWM5 P23 PWM6 P24 TM4IC SBT1 P...

Page 333: ...em clock supplied to them 3 1 CPU Modes 3 1 1 Description The MN102H75K has two CPU operating modes NORMAL and SLOW and two CPU standby modes HALT and STOP Effective use of these modes can signifi cantly reduce power consumption Figure 3 1 shows the CPU states in the different modes P72 The MN102H75K 85K provides two ways to reduce power consumption con trolling CPU operating and standby modes to ...

Page 334: ... the timing of direct memory access DMA transfers of OSD data and OSD inter rupts P191 This section describes how the MN102H75K 85K handles the timing of direct memory access DMA transfers of OSD data and OSD inter rupts P194 The MN102H75K OSD achieves a shuttering effect using four pro grammable shutters two vertical and two horizontal With this fea ture you can shutter any portion of the OSD dis...

Page 335: ...ocontroller program in an existing product B 3 Using the PROM Writer Mode In this mode the MN102HF75K allows a PROM writer to program the internal flash memory as if it was a standalone memory chip The microcontroller is inserted into a dedicated adaptor socket which con nects to DATA I O s LabSite PROM writer When the microcontroller connects to the adaptor socket it automatically enters PROM wri...

Page 336: ......

Page 337: ...Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd MN102H75K F75K 85K F85K LSI User s Manual October 2001 1st Edition 1st Printing ...

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