Panasonic BL-C30CE, Service Manual

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13.1.1. CPU Block
CPU (IC101)
Operating Power Supply: 3.3V (for I/O) 1.8V (for Core) 1.8V (for Inside PLL) 2.8V (Camera I/O)
Package: 144 pin QFD
Internal Component: 32bit RISC ARM720T, Hardware JPEG Encoder, Memory Controller, 10/100Base
Ethernet MAC, I2C I/F, Serial I/F, SRAM (48KB) and etc are built-in.
Outline of Operation: All system Control and image data from the camera is changed to JPEG data.
Then, it is changed to packet and sent out from Ethernet I/F.
32.786 KHz is entered as External Clock and increase at Internal PLL. Then, it operates at 48.955 MHz.
Flash Memory (IC102) and SDRAM (IC103) are accessed by CPU Bus.
CMOS sensor (IC701) and Real Time Clock IC (IC104) on the Camera Block are accessed by I2C I/F.
Ethernet PHY (IC201) is accessed by MII (Media Independent Interface) I/F.
FLASH MEMORY (IC102)
Operating Power Supply: +3.3V
Package: 48 pin Ball CSP
Capacity: 16Mbit
Access Time: 70ns
Outline of Operation: Stores programs for CPU operation, MAC address and customer setup data.
Version up is available from Ethernet I/F.
SDRAM (IC103)
Operating Power Supply: +3.3V
Package: 54 pin TSOP
Capacity: 64Mbit
Outline of Operation: Stores the memory for CPU work and temporary saved images.
RESET IC (IC105)
Reset voltage: 2.9V
Package: 4 pin SOP
Outline of Operation: When 3.3V power starts up, it emits about 150ms reset pulse after detecting 2.9V.
Clear Setting Button (SW104)
Outline of Operation: It is possible to bring back the setting value of a Network Camera to a factory-
shipments state, when you push.
GPI0
- Motor (PAN/TILT) Operation
- Clear Setting SW
- Privacy Mode SW
- I2C
- LED
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