Panasonic BB-HCM580A, Service Manual

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BB-HCM580A
Figure 2 Sharing of Serial Signals (SDI and SCL)
[CPU Board]
• Pixel clock and 10-bit RAW data that are output from the IC803 are transmitted to the LVDS Receiver IC (IC121) on the CPU
board via the LVDS Transmitter. In the LVDS Receiver IC (IC121), they are serial-parallel converted to recover the pixel clock
(CAM_CLK) and 10-bit RAW data (CAMD [11:2]), and the recovered pixel clock and 10-bit RAW data are entered into the CPU
(IC102).
• In the VIDEO SIGNAL Processor unit that is imbedded in IC102, the RAW data is subjected to such signal processing as OB
clamping, white balancing, and É¡ processing, then the RAW data is temporary recorded in the external SDRAM. The RAW data
is subjected to the three-step processing that is composed of pixel correction, YC generation and scaling, and the data after the
processing is recorded in the same external SDRAM as the image data.
• The synchronizing signals (CCDHD and CCDVD) and AFE control serial signals (AFE_LD, SDI, and SCL) from the CPU
(IC102), are sent to the AFE IC (IC803) on the VIDEO board via CN102 .
[LENS Board]
Camera has 21 X optical zoom lens. This lens unit has the ZOOM lens drive motor, the FOCUS lens drive motor, the IRIS unit,
and the position detection circuit for ZOOM and FOCUS lens, respectively. These components are controlled from the CPU
(IC102) on the CPU board.