Section 150-319-124
Revision 03
Page 4
3.04
The received HDSL channels are processed
by the transceiver and then passed on to the HLU-
319, List 2D demultiplexer module. The demultiplexer
provides frame synchronization for each of the two
HDSL loops. The demultiplexer and HDSL
transceivers work under control of the HLU-319, List
2D microprocessor and compensate for data
inversions caused by tip-ring reversals and loop
swaps caused by pair reversals. The HiGain system
allows for tip-ring or pair reversals, but does not
tolerate split pairs. By synchronizing to the Frame
Sync Word (FSW) of each loop, the demultiplexer can
reconstruct the original 1.544 Mbps DS1 stream from
the payloads of the two HDSL loops. The CRC fields
on the HDSL streams allow the HLU-319, List 2D to
determine if errors are present on the channel due to
excessive impairments on the HDSL pairs or
excessive impulse or crosstalk noise.
3.05
The demultiplexer removes data link
messages from the HDSL loops and passes them to
the microprocessor. This mechanism allows
operations messages and status to be exchanged
between the HLU-319, List 2D and the HRU-412
remote unit.
3.06
The reconstructed HDSL data is buffered in a
first-in-first-out (FIFO) buffer within the demultiplexer.
A frequency synthesizer, in conjunction with the FIFO,
regulates the output bit rate and reconstructs the
DSX-1 clock at the exact rate received from the
remote end. The HiGain system operates at T1 rates
of 1.544 Mbps with up to ± 200 bps of offset.
3.07
A DSX-1 interface driver converts the input
data to an Alternate Mark Inversion (AMI) or Binary
Eight Zero Substitution (B8ZS) format. The DSX-1
equalizer is programmable to five different lengths, as
determined by the distance between the HLU-319,
List 2D and the DSX-1 interface. This provides CB-
119 specification compliant pulses at the DSX-1
interface over a range of 0 to 655 feet of ABAM-
specification cable.
3.08.
The HLU-319, List 2D contains two separate
power converters. The main power supply converts
-48 Vdc local battery to logic power for the HLU-319,
List 2D circuits. The line power supply converts the
-48 Vdc battery to either 130 Vdc (for non-doubler
applications) or 200 Vdc (for doubler applications),
then provides simplex power feed on the two HDSL
line interfaces. Switch S2 allows the user to configure
the HDSL line powering voltage to be unipolar (0 to
-130 V and 0 to -200 V) or bipolar (± 65 V and ± 100
V) (see Figure 5.) The line power supply can be
turned on or off by the microprocessor and is
automatically shut down in the presence of line short
circuits or microprocessor failure.
3.09
A female 9-pin (DB-9) RS-232 connector is
provided on the front panel (see Figure 3). This
connector provides asynchronous access to the
HiGain system maintenance provisioning and
performance monitoring firmware. The port is
configured as DCE with 8 data bits, 1 stop bit and no
parity. Operator interaction with the firmware is via an
ASCII terminal or a Personal Computer with
asynchronous communication software. Striking the
Space bar several times enables the HLU-319, List
2D to automatically match the terminal line baud rate,
from 1200 to 9600 baud. Figure 7 through Figure 14
show the menu selections available from the terminal
for non-doubler applications. Figure 16 through
Figure 34 show the menu selections available from
the terminal for doubler applications. Table 8 defines
the terms used in the non-doubler System Status
screen. Table 18 defines the terms for the doubler
System Status screens.
