Version 1.0 rev 14 Aug 2019
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Balor
4.6 U
ndeRstanding
R
ead
n
oise
in
s
cMos
sCMOS technology boasts an ultra-low read noise floor that significantly exceeds that of even the best CCDs, at such
high pixel readout speeds. For those more accustomed to dealing with CCDs, it is useful to gain an understanding of the
nature of read noise distribution in CMOS imaging sensors.
CCD architecture is such that the charge from each pixel is transferred through a common readout structure, at least in
single output port CCDs, where charge is converted to voltage and amplified prior to digitization in the Analog to Digital
Converter (ADC) of the camera. This results in each pixel being subject to the same readout noise. However, CMOS
technology differs in that each individual pixel possesses its own readout structure for converting charge to voltage.
During readout, voltage information from each pixel is fed directly to the appropriate amplifier/ADC, a row of pixels at a
time (see Technical Note on Rolling and Global Shutter modes).
As a consequence of each pixel having its own individual readout structure, the overall readout noise in CMOS sensors
is described as a distribution, as exemplified in Figure 7 below, which is a representative noise histogram from a Balor. It
is standard to describe noise in CMOS technology by citing the median value of the distribution. In the data presented,
the median value is 2.6 e- RMS.
This means that 50% of pixels have a noise less than 2.6 e-, and 50% have noise greater. While there will be a small
percentage of pixels with noise greater than 6 e-, observable as the low-level tail towards the higher noise side of the
histogram.
Figure 7: Representative histogram showing read noise distribution at fastest readout speed of the Balor. The line at 6 e- represents a typical read
noise value from a well optimized Interline CCD – all pixels in a CCD essentially share the same noise value.
