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F06S/F06T 2U System Contribution

34

3.21.4

Debug Port Switch and LED

UART Debug port switch selection mode.

3.21.5

BMC Heart beat LED

Location D10

LED

Status

LED COLOR

Description

Silk Screen Label

ON

Green

BMC not ready

HEARTBEAT LED

Blink

Green

BMC Active

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Summary of Contents for QCT F06S

Page 1: ...Quanta Confidential QCT F06S F06T 19 2U 4Node 2Node System Carmel Revision 0 1 2016 1 28 Contributed by Alan Chang Quanta Computer Inc...

Page 2: ...F06S F06T 2U System Contribution 1 Revision History Revision Date Description 0 1 2016 1 28 Release for Open Compute Project...

Page 3: ...d Placement 11 2 3 2 Interposer Board Placement 12 2 4 Related Board Dimension 13 2 4 1 Sled Dimension 13 2 4 2 Motherboard Dimension 14 2 4 3 Interposer Board Dimension 14 3 PRODUCT FEATURES 15 3 1 P...

Page 4: ...sumption 32 3 20 1 Power Supply PINOUT 32 3 21 LED Definition 33 3 21 1 HDD Active LED 33 3 21 2 Power ID LED 33 3 21 3 Beep LED 33 3 21 4 Debug Port Switch and LED 34 3 21 5 BMC Heart beat LED 34 4 P...

Page 5: ...rformance 2P servers featuring Intel Grantley platform Each F06S Sled contains an OCP compliant 2P server board Facebook Server Intel motherboard v3 1 http www opencompute org wiki Motherboard SpecsAn...

Page 6: ...ideband control of Ethernet LAN Figure 1 2 F06T 2U2N System Overview 1 3 F06 OCP motherboard F06 OCP motherboard is the one used in F06S F06T Sleds and it is fully compatible with OCP 2P server board...

Page 7: ...OCP motherboard and Facebook Server Intel motherboard is as table 1 1 shown F06 OCP motherboard for F06S 2U4N F06 OCP motherboard for F06T 2U2N Facebook Server Intel motherboard Mini SAS connectors J...

Page 8: ...M PCIe Expansion Slot per node 1 PCIe x16 Gen3 riser slot for Full height Half length card per node 1 PCIe x8 Gen3 OCP mezzanine v1 card slot Rear IO per node 1 USB 3 0 port 1 GbE or 10G BASE T RJ45 p...

Page 9: ...em Contribution 8 Power Supply 2 1600W high efficiency PSU 220VAC 50 60Hz Chassis 2U chassis in 19 EIA rack Table 2 1 F06S 2U4N System Feature List 2 1 2 System Block Diagram Figure 2 1 F06S 2U4N Syst...

Page 10: ...eight Half length card 1 PCIe x8 Gen3 OCP mezzanine v1 card slot Rear IO per node 1 USB 3 0 port 1 GbE or 10G BASE T RJ45 port Front IO per node 1 Power Button 1 USB 2 0 port Network per node I210 Sin...

Page 11: ...F06S F06T 2U System Contribution 10 2 2 2 System Block Diagram Figure 2 2 F06T 2U2N System Block diagram...

Page 12: ...ETH0 RJ45 for LOM 7 J7 MSATA CONN mSATA connector 8 J4B1 PCI EX24SLOT PCIe x24 connector 9 J21 J22 J23 J24 A7 A6 A5 A4 DIMM slot for CPU0 10 U48 CPU0 CPU0 11 U64 CPU1 CPU1 12 J30 J31 J32 J33 B3 B2 B1...

Page 13: ...r board key part placement Item Ref Designator Silkscreen PCB Description 1 JP2 CONN GUIDE Guide pin for Middle plane 2 J2 B2B CONN B2B connector for Middle plane 3 J1 MINISAS HD Mini SAS HD connector...

Page 14: ...imension 2 4 1 Sled Dimension F06S Sled related dimension is 537 86mm L 21 17 x 173 75mm W 6 84 x 40 5mm H 1 59 Figure 2 5 F06S Sled dimension F06T Sled related dimension is 537 86mm L 21 17 x 173 75m...

Page 15: ...Dimension The Motherboard related dimension is 508mm L 20 x 165mm W 6 5 Figure 2 7 F06 OCP motherboard dimension 2 4 3 Interposer Board Dimension The Interposer board related dimension is 162mm L 6 3...

Page 16: ...internal voltage regulator IVR The key features are as shown below Up to 18 cores E5 2600 v3 22 cores E5 2600 v4 Up to 145W TDP Up to 10 x 4 PCIe Gen3 Support 4 channels DDR4 RDIMM LRDIMM total 16 DIM...

Page 17: ...s printed on the motherboard provide information about the channel and therefore the processor to which they belong For example DIMM_A0 is the first slot on Channel A of processor 0 DIMM_B0 is the fir...

Page 18: ...tecture The C610 PCH is capable of providing both exCLK and isCLK F06 OCP motherboard uses isCLK mode The external clock generator will not be necessary 3 6 SATA The C610 PCH supports total 10 SATA II...

Page 19: ...ws ASPEED BMC AST1250 occupies 2 USB 2 0 ports one 1 1 and one 2 0 this one is reserved for AST2400 AST1250 won t use USB2 0 channel one Rear USB3 0 port is necessary for this project one Front panel...

Page 20: ...0 Gb s one direction per lane for Gen2 8b 10b encoding and 8 0 Gb s one direction per lane for Gen3 128b 130b encoding Each port consists of a transmitter and receiver pair A link between the ports o...

Page 21: ...ls Description F06S 2U4N System per node PCIe x24 Riser 1U 1 PCIe Gen3 x16 Add on Card support OCP Mezzanine 1 PCIe Gen3 x8 Mezzanine v1 connector NCSI interface support F06T 2U2N System per node PCIe...

Page 22: ...SMDAT REFCLK3 6 7 GND GND 7 8 3 3v LAN_SMB_DAT 8 9 LAN_SMB_CLK 3 3v 9 10 3 3Vaux 3 3v 10 11 WAKE PERST 11 Mechanical Key 12 LAN_SMB_ALERT_N GND 12 13 GND REFCLK1 13 14 PETp 0 REFCLK1 14 15 PETn 0 GND...

Page 23: ...ETp 6 GND 41 42 PETn 6 GND 42 43 GND PERp 6 43 44 GND PERn 6 44 45 PETp 7 GND 45 46 PETn 7 GND 46 47 GND PERp 7 47 48 PRSNT 2 3 PERn 7 48 49 GND GND 49 50 PETp 8 SLT_CFG0 50 51 PETn 8 GND 51 52 GND PE...

Page 24: ...4 77 78 PETp 15 GND 78 79 PETn 15 GND 79 80 GND PERp 15 80 81 PRSNT 2 4 PERn 15 81 82 GND GND 82 83 PETp 16 SLT_CFG1 83 84 PETn 16 GND 84 85 GND PERp 16 85 86 GND PERn 16 86 87 PETp 17 GND 87 88 PETn...

Page 25: ...113 114 PRSNT 2 5 PERn 23 114 115 PRSNT 2 6 GND 115 Table 3 2 PIN definition of PCIe x24 Riser slot 3 9 1 2 OCP Mezzanine v1 Connector PIN Definition Pin Pin description Pin Pin description Name Name...

Page 26: ..._MEZZA_DN 88 P3E_CPU0_PCIE3_TX_C_DP8 28 GND 89 P3E_CPU0_PCIE3_TX_C_DN8 29 GND 90 GND 30 P3E_CPU0_PCIE3_RX_DP8 91 GND 31 P3E_CPU0_PCIE3_RX_DN8 92 P3E_CPU0_PCIE3_TX_C_DP9 32 GND 93 P3E_CPU0_PCIE3_TX_C_D...

Page 27: ...10 PCH SMBus interface during Sleep states S5 as well as for ME Firmware Intel I210 will be on standby power so that Wake on LAN and manageability functions can be supported Intel I210 will be used in...

Page 28: ...to motherboard to select and rotate UART console in a loop of host console BMC debug console host console so on Default console channel is on host 3 15 Fans F06 OCP motherboard supports 2 fans But sys...

Page 29: ...en HOLD DEFAULT 1 2 Disable BMC CPLD update header JP8 Pin1 8 CPLD JTAG update header HSC OCP header JP15 2 3 1 2 33A 420W 2 3 46A 587W Default MB Mate header J34 Close Close For F06 MB Open For F06C...

Page 30: ...h is connected to PCH s HOST channel and BMC SMB channel 4 Figure 3 6 F06 OCP motherboard SMB debug Header 3 17 3 BMC Debug Header J1 and J10 F06 OCP motherboard provides an interface to monitor BMC a...

Page 31: ...ion TMP75 U65 Q25 Inlet temperature sensor under F06S F06T System TMP75 U1 Q2 Outlet temperature sensor under F06S F06T System AST1250 BMC Monitor CPU System voltage and temperature Table 3 5 F06S OCP...

Page 32: ...ts must comply with the Intel Xeon E5 v3 platform SMBus architecture This is a requirement in order to minimize BIOS Firmware code development efforts and improve product board stability and debugging...

Page 33: ...in components are provided in below table Table 3 6 F06S 2U4N System power consumption Table 3 7 F06T 2U2N System power consumption 3 20 1 Power Supply PINOUT F06 motherboard Power Connector J38 Name...

Page 34: ...p The LED allows easier diagnosis in a noisy data center environment LED Status LED COLOR Description Silk Screen Label Off N A No access HDD Blink Green Hard drive activity This LED shall illuminate...

Page 35: ...tion 34 3 21 4 Debug Port Switch and LED UART Debug port switch selection mode 3 21 5 BMC Heart beat LED Location D10 LED Status LED COLOR Description Silk Screen Label ON Green BMC not ready HEARTBEA...

Page 36: ...leds and F06T is with 2x hot plug Sleds The Chassis will be enabled to complement the board offering and accommodate the marketing requirements of sled with 4 F06S sleds peripheral boards HDDs FANs PS...

Page 37: ...F06S F06T 2U System Contribution 36 Figure 4 3 F06S 2U4N system Rear View 4 2 F06T 2U2N System View Figure 4 4 F06T 2U2N System Front View...

Page 38: ...upon the feedback from OCP community 4 4 Environmental Requirements The system meets the following environmental requirements Ambient operating temperature range 0C to 35C Operating and Storage relat...

Page 39: ...for F06S system configurations Fan signals are made available via a consolidated header on Fan board and The Fan control and Fan speed monitor are by chassis management controller H8 on PDB 4 7 Front...

Page 40: ...B Certificate and Report to IEC 60950 1 2005 Second Edition and or EN 60950 1 2006 Taiwan BSMI CNS14336 94 Table 4 3 Safety Certification List USA FCC Part 15 subpart B Class A Europe EMC Directive 20...

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