Onkyo TX-SR804, Service Manual

Page: 146 / 237

TX-SR804/804E
MICROPROCESSOR TERMINAL DESCRIPTIONS -1
Q701: M30627FJPGP
Data input pin from HDMI micro prosessor
Data output pin to HDMI micro prosessor
Clock output pin to HDMI micro prosessor
Reset cotrol pin to Video Encoder/Decoder
VIDEO MUTE control pin
Data output pin to OSD
VIDEO SYNC detect pin
Clock output pin to OSD
OSD chip select pin
No use
No. Pin Name Function I/O Act. Description
1 Vref Vref
A/D Reference Voltage
2 AVcc AVcc A/D Power supply
3 P97/~ADTRG/SIN4 I
O
O H
4 P96/ANEX1/SOUT4 H
5 P95/ANEX0/CLK4 CLK
6 P94/DA1/TB4IN O H
7 P93/DA0/TB3IN
VCRST
O L
8 P92/TB2IN/SOUT3 OSDSDO O H
9 P91/TB1IN/SIN3 I H
10 P90/TB0IN/CLK3 O CLK
11 P141 ~OSDCS L
12 P140 H
13 BYTE BYTE
External bus width select pin. Connect to Ground.
14 CNVSS CNVss Processor mode select pin. Connect to the ground via resistor.
15 P87/XCIN RDSDATA I H
16 P86/XCOUT XMSRSEL
O
XM/SIRIUS select pin
17 ~RESET ~RESET I L
Reset input
18 XOUT Xout Ceramic oscillator connection pin.
19 VSS Vss
Power supply Ground pin
20 XIN Xin
21 VCC1 Vcc1 Power supply pin
22 P85/~NMI ~NMI I L
23 P84/~INT2 POFF L
Vertical sync signal detection input.
24 P83/~INT1 VSYNC I L
25 P82/~INT0
~XMERRIRQ/~RDSCLK
I L
Power failure detection input
26 P81/TA4IN/~U XMCOMSEL H
27 P80/TA4OUT/U ~XMDACRST O
H 28 P77/TA3IN ~DIRINT0
L
29 P76/TA3OUT L
30 P75/TA2IN/~W DSPBUSY H
31 P74/TA2OUT/W ~DSPINT L
32 P73/~CTS2/~RTS2/TA1IN/~V ~DSPFINT L
33 P72/CLK2/TA1OUT/V ~SDET L
34 P71/RXD2/SCL2/TA0IN/TB5IN PLLSCL CLK
35 P70/TXD2/SDA2/TA0OUT PLLSDA I/O H
36 P67/TXD1/SDA1 FTXD O H
37 Vcc1
38 P66/RXD1/SCL1 FRXD I H
39 Vss
40 P65/CLK1 FCLK O CLK
41
P64/~CTS1/~RTS1/~CTS0/CLKS1
FBUSY O H
42 P63/TXD0/SDA0 XMSRTXD O H
䇭
43 P62/RXD0/SCL0 XMSRRXD I H
䇭
44 P61/CLK0 ~XMRST O L
45 P60/~CTS0/~RTS0 ~DIRCS O L
46 P137 O H
47 P136 H
48 P135 O H
49 P134 H
50 P57/~RDY/CLKOUT ~DIRRST L
51 P56/ALE ~DSPCS L
52 P55/~HOLD ~FEPM
53 P54/~HLDA ~DSPRST O L
54 P133 O H
55 P132 O H
56 P131 MCHSEL O H
57 P130 O L
Mute output for ZONE2
58 P53/BCLK DIGCLK O
H 59 P52/~RD DIGSDI
I
CLK
60 P51/~WRH/~BHE DIGSDO O H
61 P50/~WRL/~WR ~FCE H
62 P127 O
63 P126
64 P125
O
O
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
I
VMSDI
VMSDO
VMCLK
~VMUT
SYNC
OSDCLK
Z2MUT
SBZ2MUT
H
H
H
H
H
H
DSPFCS
OSDINV
OSDINY
RDS data input from LA72725 in tuner pack
H
Ceramic oscillator connection pin.
No use
(D-type)XM IC interrupt input / (P-type)RDS clock input / (Other type)No use
Control output to XM IC
XM DAC reset pin
DIR/Codec unlock detect pin
DSP AB chip select pin
DSP C BUSY detect pin
DSP C interrupt detect pin
DSP AB interrupt detect pin
S-VIDEO detect pin
I2C clock output to tuner pack
I2C data input/output from/to tuner pack
Flash micro processor rewrite port
Flash micro processor rewrite port
Flash micro processor rewrite port
Flash micro processor rewrite port
XM/SIRIUS data output pin
XM/SIRIUS data input pin
XM IC reset pin
DIR/Codec chip select pin
OSD IC input select pin(Video)
OSD IC input select pin(S Video)
No use
No use
DIR/Codec reset control pin
DSP chip select pin
Flash micro processor rewrite port
DSP reset pin
No use
No use
Mult-ch AD Reset output
ANALOG/HDMI MCLK select pin
DIR/Codec/DSP clock output pin
DIR/Codec/DSP data input pin
DIR/Codec/DSP data output pin
Flash micro processor rewrite port
No use
Mute output for SB/ZONE2
~ADCRST
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Power supply
Power supply Ground