TX-SR604/604E/8460
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -16
Q282 : ES29LV400 (4 Mbit Flash Memory)
BLOCK DIAGRAM
Command
Register
Analog Bias
Generator
Add
re
ss Latch
BYTE#
CE#
OE#
A<0:17>
RESET#
Vcc
Vss
Chip Enable
Output Enable
Logic
Vcc Detector
Timer/
Counter
Y-Decoder
X-Decoder
Y-Decoder
Cell Array
Data Latch/
Sense Amps
Input/Output
Buffers
Sector Switches
DQ0-DQ15(A-1)
RY/BY#
Write
State
Machine
WE
#
Summary of Contents for TX-SR604
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