IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-4
Q201: CS494003CQZ (Multi-Standard Audio Decoder)-3/11
TX-SR603
X
/603E/8360
FA1, FSCDIN --- Host Address Bit One or SPI Serial Control Data input
FHS1, FRD, FR/W --- Mode Select Bit 1 or Host Parallel Output Enable or Host Parallel R/W
FHS0, FWR, FDS --- Mode Select Bit 0 or Host Write Strobe or Host Data Strobe
FCS --- Host Parallel Chip Select, Host Serial SPI Chip Select
In parallel host mode, this pin serves as the active-low chip-select input signal. In serial host
SPI mode, this pin is used as the active-low chip-select input signal.
INPUT
FHS2, FSCDIO, FSCDOUT --- Mode Select Bit 2 or Serial Control Port data Input and Output,
Parallel Port Type Select
FINTREQ --- Control Port Interrupt Request
Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has
outgoing control data that should be read by the host.
OPEN DRAIN I/O - Requires 3.3k Ohm Pull - Up
FSCLKN1, STCCLK2 --- PCM Audio Input Bit Clock
Digital-audio bit clock input. FSCLKN1 operates asynchronously from all other DSPAB clocks.
In master mode, FSCLKN1 is derived from DSPAB's internal clock generator. The active edge
of FSCLKN1 can be programmed by the DSP.
BIDIRECTIONAL - Default: INPUT
In parallel host mode, this pin serves as one of two address input pins used to select one of
four parallel resisters. In SPI serial host mode, this pin serves as the data input.
INPUT
DSPAB control port mode select bit 1. This bit is one of 3 control port select bits that are
sampled on the rising edge of RESET to determine the control port mode of DSPAB. In Intel
parallel host mode, this pin serves as the active-low data bus enable input. In Motorola parallel
host mode, this pin serves as the read-high/write-low control input signal. In serial host mode,
this pin can serve as the external memory active-low data-enable output signal.
BIDIRECTIONAL - Default: INPUT
DSPAB control port mode select bit 0. This bit is one of 3 control port select bits that are
sampled on the rising edge of RESET to determine the control port mode of DSPAB. In Intel
parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola
parallel host mode, this pin serves as the active-low data-strove-input signal. In serial host
mode, this pin can serves as the external-memory active-low write-enable output signal.
BIDIRECTIONAL - Default: INPUT
DSPAB control port mode select bit 2. This bit is one of 3 control port select bits that are
sampled on the rising edge of RESET to determine the control port mode of DSPAB. In SPI
mode this pin serves as the data output pin. In parallel host mode, this pin is sampled at the
rising edge of RESET to configure the parallel host mode as an Intel type bus or as a
Motorola type bus.
BIDIRECTIONAL - Default: INPUT
