TX-NR801/E
IC BLOCK DIAGRAMS AND DESCRIPTIONS
Block Diagram
Q103 AK4528VF(24 bit 96 kHz Audio CODEC)
VCOM
SDTO
BICK
LRCK
DGND
VT
VD
DATT
SMUTE
DEM1
DEM0
PDN
SDTI
Audio I/F
Controller
HPF
ADC
DAC
Clock Divider
Control Register I/F
AINL+
AINL-
AINR+
AINR-
AOUTL+
AOUTL-
AOUTR+
AOUTR-
VREF
VA
AGND
P/S
CSN CCLK CDTI
(DIF) (CKS1) (CKS0)
MCLK DFS
No.
Pin Name
I/O
O
2
AINR+
I
3
AINR-
I
4
AINL +
I
5
AINL -
I
6
VREF
I
7
AGND
-
8
VA
-
9
P/S
10
MCLK
I
11
LRCK
I
12
BICK
I
Audio Serial Data Clock Pin.
13
SDTO
O
14
SDTI
I
CDTI
I
15
CKS0
I
CCLK
I
16
CKS1
I
CSN
I
17
DIF
I
2
18
DFS
I
19
PDN
I
20
DEM0
I
21
DEM1
I
22
VT
-
23
VD
-
24
DGND
-
25
AOUTL-
O
26
AOUTL+
O
27
AOUTR-
O
28
AOUTR+
O
Function
Common Voltage Output Pin,VA/2.
Bias voltage of ADC inputs and DAC outputs.
Rch Positive Input Pin.
Rch Negative Input Pin.
Lch Positive Input Pin,
Lch Negative input Pin.
Lch Negative Analog Output Pin.
Lch Positive Analog Output PIn.
Rch Negative Analog Output Pin.
Rch Positive Analog Output PIn.
Digital Ground Pin
De-emphasis Control Pin
De-emphasis Control Pin
Output Buffer Power Supply Pin,2.7~5.25V
Digital Power Supply Pin, 4.75~5.25V.
Voltage Reference Input Pin,VA.
Used as a voltage reference by ADC & DAC,VREF is connected
externally to filtered VA.
Analog Ground Pin
Analog Power Supply Pin,4.75~5.25V.
Parallel/Serial Mode Select Pin.
"L":Serial Mode,"H":Parallel Mode
Master Clock Input Pin
Input/Output Channel Clock Pin
Audio Serial Data Input Pin.
Audio Serial Data Output Pin.
Control Data Input Pin in Serial Mode.
Master Clock Select Pin.
Control Data Clock Pin in Serial Mode.
Master Clock Select Pin.
Chip Select Pin in Serial Mode.
Digital Audio Interface Select Pin,
"L":24bit MSB justified,"H":I S compatible.
Double Speed Sampling Mode Pin.
Power-Down Mode Pin.
"H":Power up, "L":Power down reset and initialize the control register.
1
VOM
I
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