IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -21
Q281: IC42S16100 (16-Mbit Synchronous Dynamic RAM)
BLOCK DIAGRAM
TX-SR604/604E/8460
PIN CONFIGURATION
1
CLK
CKE
CS
RAS
CAS
WE
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MULTIPLEXER
ROW
ADDRESS
BUFFER
ROW
ADDRESS
BUFFER
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
ROW DECODER
ROW DECODER
11
11
11
11
8
11
11
MEMORY CELL
ARRAY
BANK 0
COLUMN DECODER
MEMORY CELL
ARRAY
BANK 1
SENSE AMP I/O GATE
SENSE AMP I/O GATE
2048
2048
8
256
256
DATA IN
BUFFER
DATA OUT
BUFFER
DQM
I/O 0-15
Vcc/VccQ
GND/GNDQ
16
16
16
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VCC
I/O0
I/O1
GNDQ
I/O2
I/O3
VCCQ
I/O4
I/O5
GNDQ
I/O6
I/O7
VCCQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
GNDQ
I/O13
I/O12
VCCQ
I/O11
I/O10
GNDQ
I/O9
I/O8
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
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