TX-SR604/604E/8460
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS -5
Pin
Mnemonic
Input/Output
Function
40, 47, 53, 56,
63
41, 43, 45, 57,
59, 61
42, 44, 46, 58,
60, 62
48, 49
50
51
52
54, 55
64
65
66
67
68
69
70
79
80
AVSS
AVSS1-6
AIN1-6
CAPY1-2
AVDD
REFOUT
CML
CAPC1-2
ISO
ALSB
SDATA
SCLK
VREF/VRESET
HREF/HRESET
FIELD
G
G
I
I
P
O
O
I
I/O
I
I
I/O
I
O
O
I
O
I
O
Ground for Analog Supply
Analog Input Channels. Ground if single-ended mode is selected. These
pins should be connected directly to REFOUT when differential mode is
selected.
ADC Capacitor Network
Analog Supply Voltage (5 V)
Internal Voltage Reference Output
Common-Mode Level for ADC
ADC Capacitor Network
System Reset Input. Active Low.
Input Switch Over. A low to high transition on this input indicates to the
decoder core that the input video source has been changed externally and
configures the decoder to reacquire the new timing information of the new
source. This is useful in applications where external video muxes are used.
This input gives the advantage of faster locking to the external muxed
video sources. A low to high transition triggers this input.
TTL Address Input. Selects the MPU address:
MPU address = 88h ALSB = 0, disables I C filter
2
MPU address = 8Ah ALSB = 1, enables I C filter
2
MPU Port Serial Data Input/Output
MPU Port Serial Interface Clock Input
VREF or Vertical Reference Output Signal. Indicates start of next field.
VRESET or Vertical Reset Output is a signal that indicates the beginning
of a new field. In SCAPI/CAPI mode this signal is one clock wide and
active low relative to CLKIN. It immediately follows the HRESET pixel,
and indicates that the next active pixel is the first active pixel of the next field.
HREF or Horizontal Reference Output Signal. A dual-function pin
(enabled when Line-Locked Interface is selected, OM_SEL[1:0] = 0,0),
this signal is used to indicate data on the YUV output. The positive slope
indicates the beginning of a new active line; HREF is always 720 Y samples
long. HRESET or Horizontal Reset Output (enabled when SCAPI or
CAPI is selected, OM_SEL[1:0] = 0, 1 or 1, 0) is a signal that indicates the
beginning of a new line of video. In SCAPI/CAPI this signal is one clock
cycle wide and is output relative to CLKIN. It immediately follows the last
active pixel of a line. The polarity is controlled via PHVR.
Asynchronous FIFO Read Enable Signal. A logical high on this pin enables
a read from the output of the FIFO.
Output Enable Controls Pixel Port Outputs. A logic high will three-state
P19-P0.
ODD/EVEN Field Output Signal. An active state indicates that an even
field is being digitized. The polarity of this signal is controlled by the PF bit.
Video Analog Input Channels
DV or Data Valid Output Signal. In SCAPI/CAPI mode, DV performs to
functions, depending on whether SCAPI or CAPI is selected. It toggles
high when the FIFO has reached the AFF margin set by the user, and
remains high until the FIFO is empty. The alternative mode is where it can
be used to control FIFO reads for bursting information out of the FIFO. In
API mode DV indicates valid data in the FIFO, which includes both pixel
information and control codes. The polarity of this pin is controlled via PDV.
OE
RESET
Q4001: ADV7183
(Advanced Video Decoder with 10-Bit ADC and Component Input Support)
TERMINAL DESCRIPTION (2/2)
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