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TX-SR506
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-6
Q281
: M12L64164A-7TG (
1M x 16 Bit x 4 Banks Synchronous DRAM)
BLOCK DIAGRAM
PIN LAYOUT
TERMINAL DESCRIPTION
L(U)DQM
DQ
Bank D
Bank B
Bank C
Address
CLK
CKE
CS
RAS
CAS
WE
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Data Control Circuit
Row Decoder
Bank A
Sense Amplifier
Column Decoder
Latch Circuit
Input & Output
Buffer
Mode
Register
Control Logic
Command Decoder
Clock
Generator
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
A13
A12
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
TOP VIEW
Description
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except CLK , CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7.
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with CAS low. Enables column access.
Enables write operation and row precharge. Latches data in starting from CAS , WE active.
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
This pin is recommended to be left No Connection on the device.
Pin Name
CLK
CS
CKE
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
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