TX-SR505/505E
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-17
Q8003 : AD8196 (HDMI/DVI Switch with Equalization)-1/2
PIN LAYOUT
BLOCK DIAGRAM
AVCC
DVCC
AMUXVCC
AVEE
DVEE
VTTO
OP[3:0]
AUX_COM[3:0]
I2C_SDA
I2C_SCL
I2C_ADDR
ON[3:0]
+
–
4
4
4
4
4
AD8196
RESET
CONTROL
LOGIC
CONFIG
INTERFACE
SERIAL INTERFACE
VTTI
IP_A[3:0]
IN_A[3:0]
+
–
4
4
VTTI
IP_B[3:0]
IN_B[3:0]
+
–
4
4
PE
EQ
SWITCH
CORE
AUX_A[3:0]
AUX_B[3:0]
BIDIRECTIONAL
SWITCH
CORE
1
AVCC
2
IN_A0
3
IP_A0
4
AVEE
5
IN_A1
6
IP_A1
7
VTTI
8
IN_A2
9
IP_A2
10
AVCC
11
IN_A3
12
IP_A3
13
AVEE
14
I2C_ADDR
35 IP_B1
36 VTTI
37 IN_B2
38 IP_B2
39 AVEE
40 IN_B3
41 IP_B3
42 AVCC
34 IN_B1
33 AVCC
32 IP_B0
31 IN_B0
30 AVEE
29 I2C_SDA
15
DVCC
16
ON0
17
OP0
19
ON1
21
DVCC
20
OP1
22
ON2
23
OP2
24
VTTO
25
ON3
26
OP3
27
RESET
28
I2C_SCL
18
VTTO
45
AUX_B1
46
AUX_B0
47
AMUXVCC
48
AUX_COM3
49
AUX_COM2
50
AUX_COM1
51
AUX_COM0
52
DVEE
53
AUX_A3
54
AUX_A2
44
AUX_B2
43
AUX_B3
TOP VIEW
(Not to Scale)
AD8196
55
AUX_A1
56
AUX_A0
HIGH SPEED
BUFFERED
LOW SPEED
UNBUFFRED
