DV-SP500
ICs BLOCK DIAGRAM / TERMINAL DESCRIPTION
1
BCK
16
SCK
2
DATA
15
ML
3
LRCK
14
MC
4
DGND
13
MD
5
V
DD
12
ZEROL/NA
6
V
CC
11
ZEROR/ZEROA
7
V
OUT
L
10
V
COM
8
V
OUT
R
9
AGND
Audio
Serial
Port
Enhanced
Multi-level
Delta-Sigma
Modulator
4´ / 8´
Oversampling
Digital Filter
with
Function
Controller
Serial
Control
Port
BCK 1
LRCK 3
DATA 2
ML 15
MC 14
DAC
Output Amp and
Low-pass Filter
DAC
Power Supply
Output Amp and
Low-pass Filter
V
OUT
L
7
V
OUT
R
8
AGND
8
V
CC
6
DGND
9
V
DD
ZEROR/ZEROA
5
11
ZEROL/NA
12
V
COM
10
Zero Detect
No.
Name
I/O
Pin Function
1
BCK
I
Audio data bit clock input
2
DATA
I
Audio data digital input
3
LRCK
I
L-channel and R-channel Audio data
latch enable input
4
DGND
-
Digital ground
5
V
DD
-
Digital power 3.3V
6
V
CC
-
Analog power 5V
7
V
OUT
L
O
Analog output for L-channel
8
V
OUT
R
O
Analog output for R-channel
9
AGND
-
Analog ground
10
V
COM
-
Common voltage decoupling
11
ZEROR/ZEROA
O
Zero flag output for R-channel / Zero
flag output for L/R-channel
12
ZEROL/NA
O
Zero flag output for L-channel / No
assign
13
MD
I
Mode control data input
14
MC
I
Mode control clock input
15
ML
I
Mode control latch input
16
SCK
I
System clock input
Q301 : PCM1742KE (Digital/ Analog signal converter)
Block diagram
Terminal Description
Pin layout
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9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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