Q1852: K4S281632K-UC60 SDRAM
Bank Select
Data Input Register
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Sense AMP
O
utput Buf
fer
I/O Control
Column Decoder
Latency & Burst Length
Programming Register
Addre
s
s Register
Row Buf
fer
Refresh Co
unter
Row Deco
d
er
Col. Buf
fer
LRAS
LCBR
LCKE
M
Q
D
L
E
W
L
R
B
C
L
S
A
R
L
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Timing Register
FUNCTIONAL BLOCK DIAGRAM
C-S5VL
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
