One Stop Systems EB3200, User Manual

Page: 81 / 85

One Stop Systems
ExpressBox 3200 | 9 Appendix B PCI Express General Information 81
9.6 Bandwidth
There are several different versions of PCIe interface with different bandwidth limitations. CPU motherboards have PCIe slots of different
physical sizes, lanes and different PCIe generations.
A single PCIe 1.0 lane can carry up to 2.5 Gigatransfers per second (GTs) in each direction simultaneously. For PCIe 2.0, that increases to 5GT/s,
and a single PCIe 3.0 lane can carry 8GT/s.
Gigatransfers per second are the same thing as gigabits per second, but they include the bits that are lost as a result of interface overhead. All
PCI Express versions lose some of their theoretical maximum throughput to the physical overhead associated with electronic transmission.
PCIe 1 and 2.0 use 8b/10b encoding, the upshot of which is that 8 bits of data cost 10 bits to transmit, so they lose 20 percent of their
theoretical bandwidth to overhead. After overhead, the maximum per lane data rate of PCIe 1.0 is eighty percent of 2.5GT/s, which gives
2gigabits per second or 250MB/s (8bits to a byte). The PCIe interface is bidirectional, so that is 250MB/s in each direction per lane. PCIe 2.0
doubles the per-lane throughput to 5GT/s, which gives 500MB/s of actual data transfer per lane.
PCIe 3.0 is twice the speed of PCIe 2.0, having a per lane throughput that is only 60 percent more than PCIe 2.0’s 5GT/s. PCIe 3.0 use more
efficient encoding scheme called 128b/130b, so the overhead is much less, only 1.54 percent. This means that a single PCIe 3.0 lane, at 8GT/s,
can send 985B/s.
A PCIe 3.0 x4 connection (3.94GB/s) should have nearly the same bandwidth as PCIe 1.1 x16 or PCIe 2.0 x8 (both 4GB/s)
For example, two PCIe 3.0 GPUs running at x8 each on a PCIe 3.0 motherboard should have almost the same bandwidth as two PCIe 2.0 GPUs
running at x16
The lower number of PCIe lanes available determines the speed or performance of your connection. This means if your motherboard or PCIe
card is limited to a PCIe 1.0 or 2.0 connections, you are basically stuck using a slower interface.
9.7 Operation Mode
The PCI Express connection is based on the number of “lanes” availability, which is a single-bit, full-duplex, high-speed serial communication.
Lanes can be grouped to increase bandwidth. For example, when two devices use four lanes for their connection, they are considered an “x4”
connection and will be able to achieve four times more bandwidth than a single connection, i.e., a single lane. Photo below illustrates two
connected devices using two lanes, i.e., an “x2” connection. Although in theory any number from one to 32 lanes can be grouped, the most
common numbers are x4, x8, and x16.