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EVBUM2565/D

www.onsemi.com

6

SWJ

DP DEBUG Port

The J

Link adapters are typically used to communicate

with RSL10 SIP using the standard Coresight SWJ

DP

debug port in a JTAG/SW communication protocol. The
9-pin 0.05 in Samtec FTSH header (

P1

), defined by the

Arm Cortex

M3 core on the board, connects RSL10 SIP to

external adapters compatible with the Arm Cortex

M3

processor’s SWJ

DP interface. Alternatively, you can

connect the micro USB port on the board to a PC.

DIGITAL Input/Output (DIO)

The RSL10 SIP contains 16 digital I/O (DIO) signals.

The DIO voltage domain is VDDO, while the input voltage
can be VBAT or external voltage as outlined in Section
“Measuring the Current Consumption” on page 5.

The DIO signals on the RSL10 SIP are multiplexed with

several interfaces, including:

One I

2

C interface (

DIO [7:8]

)

Four external inputs to the low-speed analog to digital
converters (

DIO [0:3]

)

One PCM interface

Two PWM drivers

Two SPI interfaces (

DIO [13:15]

)

One UART interface (

DIO [4:5]

)

Support interfaces that can be used to monitor control
of the RF front-end and Bluetooth

®

 

baseband controller

For more information about the DIO multiplexed signals,

refer to the 

RSL10 Hardware Reference

.

The board provides access to any of the DIOs or their

multiplexed signals via the Arduino Headers (

Power1

,

AD1

IOL1

, and 

IOH1

).

The LED circuit provides visual monitoring of the DIOs;

refer to Section “LED Circuitry” on page 5 for further
information.

Power Supplies

There are several external power supplies available on

your Evaluation and Development Board.

The user can also access signals on various headers on

boards, as described throughout this document.

The external power supplies available for QFN boards

are:

VBUS, 5 V from USB connection 

 available only

when USB is plugged in

V3.3, 3.3 V from LDO 

 available when regulated

supply is selected

VEXT, (

P5

 header) unregulated external supply 

available when unregulated supply is selected

Battery (

J5

 Battery Holder, 12 mm coin cell battery)

Downloaded from

Arrow.com.

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Arrow.com.

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Summary of Contents for RSL10 SIP

Page 1: ...of the parts that are used to manufacture the Evaluation and Development Board Further Reading For more information refer to the following documents Getting Started with RSL10 RSL10 Firmware Referenc...

Page 2: ...rd one connect the debugger to connector P2 on the SiP board as shown in Figure 2 Notice that for this setup you also need a power supply Figure 2 Evaluation and Development Board Setup with External...

Page 3: ...M2565 D www onsemi com 3 Figure 3 Circuit Location Block Diagram Top View Figure 4 Circuit Location Block Diagram Bottom View Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

Page 4: ...igure 5 Three Dimensional Line Drawing of the Board Top View Figure 6 Three Dimensional Line Drawing of the Board Bottom View Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

Page 5: ...ndependent VDDO can be equal to or less than 3 3 V when connected to the power rail To enable the level translators populate positions R34 and R35 with 0 ohms By default the level translators are disa...

Page 6: ...face DIO 4 5 Support interfaces that can be used to monitor control of the RF front end and Bluetooth baseband controller For more information about the DIO multiplexed signals refer to the RSL10 Hard...

Page 7: ...on POWER1 Arduino Power header 3 3 V VDDO nRESET GND AD1 Arduino Analog Inputs header A 0 3 IOL1 Arduino IOL header UART INT 0 1 SPI2 IOH1 Arduino IOH header I2C SPI1 P2 External JTAG debug connection...

Page 8: ...GND TRSTin TDIin TMSin TCKin TRESin TDOin DIO4 DIO5 U_Interface MCU Interface MCU SchDoc DIO0 DIO1 DIO2 DIO3 DIO6 DIO 15 0 DIO13 DIO14 DIO15 DIO10 DIO11 DIO12 U_Power Power SchDoc VDDO 5V VIN3 3V 2 1...

Page 9: ...DIO14 DIO15 OUT_ANT F1 OUT_MOD E1 DIO0 C7 DIO1 B6 DIO2 A7 DIO3 A6 DIO4 B8 DIO5 A8 DIO6 A5 DIO7 B7 DIO8 B5 DIO9 C2 DIO10 A4 DIO11 B3 DIO12 A2 DIO13 B1 DIO15 C1 AOUT E8 WAKEUP F8 EN_TEST F7 NRESET E7 E...

Page 10: ...NDBU 46 GND 61 GNDPLL 72 GNDUTMI 82 GND 89 VDDCORE 9 VDDCORE 34 VDDCORE 59 VDDCORE 87 VDDBU 45 VDDIN 53 VDDANA 1 VDDIO 22 VDDIO 36 VDDIO 60 VDDIO 88 VDDOUT 52 VDDPLL 73 VDDCORE 83 VDDUTMI 79 U2 ATSAM3...

Page 11: ...P9 VDD_AT Select VDDO Select Optional Level Shifter 2 1 P5 2 1 P3 2 1 3 P7 2 1 3 P10 VBAT VBAT Select 3 3V Select POWER OPTIONS EXTERNAL POWER CURRENT VREG POWER SUPPLY CONFIGURATION HEADERS P4 P7 P10...

Page 12: ...ADER 10POS DUAL 05 SMD KEYING SHROUD FTSH 105 P3 P5 HEADER 2POS 1ROW Series 961 Pitch Spacing 2 54 mm RA P6 2x4 Pin Header P7 P8 P9 P10 HEADER 3POS 1ROW Series 961 Pitch Spacing 2 54 mm Q1 NMOS Transi...

Page 13: ...experts ON Semiconductor does not convey any license under its patent rights nor the rights of others ON Semiconductor products are not designed intended or authorized for use as a critical component...

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