background image

EVBUM2565/D

www.onsemi.com

10

Figure 9. Interface MCU Schematic

NRSTB

47

PA0/TIOB0/NPCS1

26

PA1/TIOA0/NPCS2

27

PA10/TWCK0/PWML3

39

PA11/URXD/PWMFI0

40

PA12/UTXD/PWMFI1

41

PA13/MISO

10

PA14/MOSI

11

PA15/SPCK/PWMH2

12

PA16/NPCS0/N

C

S1

13

PA17/SCK0/ADTRG

14

PA18/TXD0/PWMFI2

17

PA19/RXD0/NPCS3

18

PA2/TCLK0/AD12BTRG

28

PA20/TXD1/PWMH3

19

PA21/RXD1/PCK0

20

PA22/TXD2/R

TS1/AD12B0

5

PA23/RXD2/CTS1

21

PA24/TWD1/SCK1

23

PA25/TWCK1/SCK2

24

PA26/TD/TCLK2

25

RD/PCK0/PA27

96

TK/PWMH0/PA28

84

RK/PWMH1/PA29

85

PA3/MCCK/PCK1

29

PA30/TF/TIOA2/AD12B1

6

PA4/MCCDA/PWMH0

30

PA5/MCDA0/PWMH1

31

PA6/MCDA1/PWMH2

32

PA7/MCDA2/PWML0

33

PA8/MCDA3/PWML1

37

PA9/TWD0/PWML2

38

PWMH0/A2/PB0

90

PWMH1/A3/PB1

91

D1/D

SR0/

PB10

70

D2/DCD0/PB11

93

D3/RI0/PB12

94

D4/PWMH0/PB13

95

D5/PWMH1/

PB14

69

PB15/D6/PWMH2

16

PB16/D7/PWMH3

15

NANDOE/PWML0/

PB17

68

NANDWE/PWML1/

PB18

67

NRD/PWML2/

PB19

66

PWMH2/A4/PB2

92

N

C

S0/PWML3/

PB20

65

A21(NANDALE/R

TS2/

PB21

64

A22/NANDCLE/CTS2/

PB22

63

NWR0/NWE/PCK2/

PB23

62

NANDRDY/PCK1/

PB24

58

AD12BVREF

4

DHSDP

76

DHSDM

77

VBG

78

DFSDM

80

PB3/PWMH3/A5/AD12BAB2

7

DFSDP

81

PB4/TCLK1/A6/AD12BAB3

8

TIOA1/A7/AD0/PB5

97

TIOB1/D15/AD1/PB6

98

RTS0/A0/NBS0/AD2/PB7

99

CTS0/A1/AD3/PB8

100

D0/DTR0/

PB

9

71

RF/TIOB2/PA31

86

ADVREF

2

XIN32

50

XOUT32

49

ERASE

43

NRST

57

FWUP

42

XIN

75

XOUT

74

TEST

44

JTAGSEL

48

TCK

56

TDI

51

TDO

54

TMS

55

GNDANA

3

GND

35

GNDBU

46

GND

61

GNDPLL

72

GNDUTMI

82

GND

89

VDDCORE

9

VDDCORE

34

VDDCORE

59

VDDCORE

87

VDDBU

45

VDDIN

53

VDDANA

1

VDDIO

22

VDDIO

36

VDDIO

60

VDDIO

88

VDDOUT

52

VDDPLL

73

VDDCORE

83

VDDUTMI

79

U2 A

TSAM3U2CA

AU

VDD_A

T

GND

VDD_A

T

TCKin

R21 0

C30 100nF

VCORE

TDIin

T

M

Sin

TCKout

T

M

Sout

TDIout TDOin ENSPI

VDD_A

T

TCKout

0

R26 DNP

0

R27 DNP

C38 100nF

C39 100nF

VDD_A

T

C37 100nF

VDD_A

T

R29 6k8

C36 100nF

IMCU_TDIS

IMCU_TDOS

IMCU_TMSS

IMCU_TCKS

IMCU_RESET

C35 10

μ

F

VCORE

C34 10

μ

F

C33 100nF

VDD_A

T

C31 100nF

C32 100nF

VCORE

VDD_A

T

C29 100nF

VCORE

X3 12MHz

C26

18pF

C28

18pF

C22 10pF

R18 6k8

C23 100nF

VDD_A

T

C18 100nF

VCORE

C19 100nF

VCORE

C21 100nF

R19

6k8

ENSPI

VBUS

1

D

2

D+

3

GND

5

ID

4

Shield

J2

M

ic

roUSB

B

C20 100nF

R17 6k8

GND

1

IO1

2

VCC

4

IO2

3

D1

PR

TR5V0U2X

C24 10

μ

F

R10

39

R1

1

39

D

FSD_P

D

FSD_N

DHSD_N DHSD_P

1

10

2

9

3

7

4

6

5

8

J3

TC2050

IDC

R12 4k7

R13 4k7

R14 4k7

R20 4k7

VDD_A

T

VDD_A

T

VBUS

VBUS

IMCU_TMSS

IMCU_TCKS

IMCU_TDOS IMCU_TDIS IMCU_RESET

R22

150

R23

150

R24

150

R25

150

R28

150

TRST

out

TRST

in

TDIout

TDIin

T

M

Sout

T

M

Sin

TCKout

TCKin

TRESout

TRESin

TDOin

TRST

in

TDIin

T

M

Sin

TCKin

TRESin

TDOin

R

G

LD1 LTST

C195KGJRKT

R15 220

R16 220

VDD_A

T

C25 100nF

C27 100nF

DIO4

DIO5

R30

68

R31

68

DIO4

DIO5

DHSD_N

DHSD_P

DFSD_N

DFSD_P

TRSTin

TRESin

TRSTout

TRESout

CTS

RTS

RxD

TxD

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Summary of Contents for RSL10 SIP

Page 1: ...of the parts that are used to manufacture the Evaluation and Development Board Further Reading For more information refer to the following documents Getting Started with RSL10 RSL10 Firmware Referenc...

Page 2: ...rd one connect the debugger to connector P2 on the SiP board as shown in Figure 2 Notice that for this setup you also need a power supply Figure 2 Evaluation and Development Board Setup with External...

Page 3: ...M2565 D www onsemi com 3 Figure 3 Circuit Location Block Diagram Top View Figure 4 Circuit Location Block Diagram Bottom View Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

Page 4: ...igure 5 Three Dimensional Line Drawing of the Board Top View Figure 6 Three Dimensional Line Drawing of the Board Bottom View Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

Page 5: ...ndependent VDDO can be equal to or less than 3 3 V when connected to the power rail To enable the level translators populate positions R34 and R35 with 0 ohms By default the level translators are disa...

Page 6: ...face DIO 4 5 Support interfaces that can be used to monitor control of the RF front end and Bluetooth baseband controller For more information about the DIO multiplexed signals refer to the RSL10 Hard...

Page 7: ...on POWER1 Arduino Power header 3 3 V VDDO nRESET GND AD1 Arduino Analog Inputs header A 0 3 IOL1 Arduino IOL header UART INT 0 1 SPI2 IOH1 Arduino IOH header I2C SPI1 P2 External JTAG debug connection...

Page 8: ...GND TRSTin TDIin TMSin TCKin TRESin TDOin DIO4 DIO5 U_Interface MCU Interface MCU SchDoc DIO0 DIO1 DIO2 DIO3 DIO6 DIO 15 0 DIO13 DIO14 DIO15 DIO10 DIO11 DIO12 U_Power Power SchDoc VDDO 5V VIN3 3V 2 1...

Page 9: ...DIO14 DIO15 OUT_ANT F1 OUT_MOD E1 DIO0 C7 DIO1 B6 DIO2 A7 DIO3 A6 DIO4 B8 DIO5 A8 DIO6 A5 DIO7 B7 DIO8 B5 DIO9 C2 DIO10 A4 DIO11 B3 DIO12 A2 DIO13 B1 DIO15 C1 AOUT E8 WAKEUP F8 EN_TEST F7 NRESET E7 E...

Page 10: ...NDBU 46 GND 61 GNDPLL 72 GNDUTMI 82 GND 89 VDDCORE 9 VDDCORE 34 VDDCORE 59 VDDCORE 87 VDDBU 45 VDDIN 53 VDDANA 1 VDDIO 22 VDDIO 36 VDDIO 60 VDDIO 88 VDDOUT 52 VDDPLL 73 VDDCORE 83 VDDUTMI 79 U2 ATSAM3...

Page 11: ...P9 VDD_AT Select VDDO Select Optional Level Shifter 2 1 P5 2 1 P3 2 1 3 P7 2 1 3 P10 VBAT VBAT Select 3 3V Select POWER OPTIONS EXTERNAL POWER CURRENT VREG POWER SUPPLY CONFIGURATION HEADERS P4 P7 P10...

Page 12: ...ADER 10POS DUAL 05 SMD KEYING SHROUD FTSH 105 P3 P5 HEADER 2POS 1ROW Series 961 Pitch Spacing 2 54 mm RA P6 2x4 Pin Header P7 P8 P9 P10 HEADER 3POS 1ROW Series 961 Pitch Spacing 2 54 mm Q1 NMOS Transi...

Page 13: ...experts ON Semiconductor does not convey any license under its patent rights nor the rights of others ON Semiconductor products are not designed intended or authorized for use as a critical component...

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