NCS36000
5
1
+
−
2
3
+
−
4
5
G
D
VREF
LDO
6
Sensor dependent
components
Vm
VREF 6
Vm
Vh
Vl
Application dependent
components
+
−
Vl
Vh
OP2_O
+
−
Comp_P
Comp_N
Figure 5. Figure Showing Simplified Block Diagram of Analog Conditioning Stages
Digital Signal Processing Block (all times assume a
62.5 Hz system oscillator frequency)
The digital signaling processing block performs three
major functions.
The first function is that the device toggles LED during the
start−up sequencing at approximately two hertz regardless
of the state of the XLED_EN pin. The startup sequence lasts
for thirty seconds. During that time the OUT pin is held low
regardless of the state of OP2_O.
The second function of the digital signal processing block
is to insure a certain glitch width is seen before OUT is
toggled. The digital signal processing block is synchronous
with the system oscillator frequency and therefore the
deglitch time is related to when the comparators toggle
within the oscillator period. A signal width less than two
clock period is guaranteed to be deglitched as a zero. A
signal width of greater than three clock cycles is guaranteed
to be de−glitched. It should be noted that down−sampling
can occur if sufficient anti−aliasing is not performed at the
input of the circuit (OPI_P) or if noise is injected into the
amplifiers, an example would be a noisy power supply.
The third function of the digital signal processing block is
to recognize different pulse signatures coming from the
window comparator block. The device is equipped with two
pulse recognition routines. Single pulse mode (MODE tied
to VSS) will trigger the OUT pin if either comparator toggles
and the deglitch time is of the appropriate length. (See
Figure 6). Dual pulse mode (MODE tied to V
DD
) requires
two pulses with each pulse coming from the opposite
comparator to occur within a timeout window of five
seconds or 312 clock cycles (See Figure 7). If the adjacent
pulses occur outside the timeout window then the digital
processing block will restart the pulse recognition routine.
xLED_EN Pin
The xLED_EN pin enables the LED output driver when
motion has been detected. If xLED_EN is tied high the LED
pin will not toggle after motion is detected. If the xLED_EN
is tied low the LED pin will toggle when motion is detected.
During start-up the LED pin will toggle irrespective of how
the xLED_EN pin is tied. (See Figure 6).
Figure 6. Timing Diagram for Single−Pulse Mode Detection
T
SP
< 3T
CLK
OP 2_O
V
H
= 2,5V
T
SP
> 3T
CLK
OUT
120 T
CLK
4T
CLK
V
L
= 1,7V
V
M
= 2,1V
