NCP1060, NCV1060, NCP1063, NCV1063
www.onsemi.com
22
Figure 39. Ipk set−point is frozen at lower power demand (I
LMOP
≥
285
m
A)
0
50
100
150
200
250
300
350
40
50
60
70
80
90
100
110
Current set point [mA]
I
COMP
[
m
A]
NCP1060
NCP1063
Feedback and Skip
Figure 40 depicts the relationship between COMP pin
voltage and current. The COMP pin operates linearly as the
absolute value of COMP current (I
COMP
) is above 40
m
A. In
this linear operating range, the dynamic resistance is
17.7 k
W
typically (R
COMP(up)
) and the effective pull up
voltage is 2.7 V typically (V
COMP(REF)
). When I
COMP
is
decreases, the COMP voltage will increase to 3.2 V.
Figure 40. COMP Pin Voltage vs. Current
0
0.5
1
1.5
2
2.5
3
3.5
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
V
COMP
[V]
I
COMP
[
μA
]
Figure 41 depicts the skip mode block diagram. When the
COMP current information reaches I
COMPskip
, the internal
clock setting the flip−flop is blanked and the internal
consumption of the controller is decreased. The hysteresis of
internal skip comparator is minimized to lower the ripple of
the auxiliary voltage for V
CC
pin and V
OUT
of power supply
during skip mode. It easies the design of V
CC
over load
range.
