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ECLSOIC8EVB

http://onsemi.com

4

Evaluation Board Assembly Instructions

The 8

lead SOIC evaluation board is designed for

characterizing devices in a 50 

W

 laboratory environment

using high bandwidth equipment. Each signal trace on the
board has a via, which has an option of termination resistor
or bypassing capacitor depending on the input/output
configuration (see Table 1. Configuration List). Table 17
contains the Bill of Materials for this evaluation board.

Solder the Device on the Evaluation Board

The soldering can be accomplished by hand soldering or

soldering re

flow techniques. Make sure pin 1 of the device

is located next the white dotted mark U1 and all the pins are
aligned to the footprint pads. Solder the 8

lead SOIC device

to the evaluation board.

Connecting Power and Ground Planes

For standard ECL lab setup and test, a split (dual) power

supply is required enabling the 50

 W

 internal impedance in

the oscilloscope to be used as a termination of the ECL
signals (V

TT

 = V

CC

 – 2.0 V, in split power supply setup, V

TT

is the system ground, V

CC

 is 2.0 V, and V

EE

 is –3.0 V or

–1.3 V; see Table 2: Power Supply Levels).

Table 2. Power Supply Levels

Power Supply

V

CC

V

EE

GND

5.0 V

2.0 V

3.0 V

0.0 V

3.3 V

2.0 V

1.3 V

0.0 V

2.5 V

2.0 V

0.5 V

0.0 V

The power supply for voltage level translating device need
slight modification as indicated in Table 3. Power Supply
Levels for Translators.

Table 3. Power Supply Levels for Translators

V

CC

V

EE

GND

PECL Translators

3.3 V / 5.0 V

0.0 V

0.0 V

On the top side of the evaluation board solder the four

surface mount test point clips to the pads labeled V

CC

, V

EE

,

and GND. The V

CC

 clip connects directly to pin 8 of the

device. The V

EE

 clip connects directly to pin 5 of the device.

There are two GND clip footprints which can be connected
to the ground plane of the evaluation board depending on the
setup configuration.

It is recommended to solder 0.01 

m

F capacitors to C1 and

C2 to reduce the unwanted noise from the power supplies.
C3 and C4 pads are provided for 0.1 

m

F capacitor to further

diminish the noise from the power supplies. Adding
capacitors can improve edge rates, reduce overshoot and
undershoot.

Termination

All ECL outputs need to be terminated to V

TT

 (V

TT

 = V

CC

–2.0 V = GND) via a 50 

W

 resistor in a split power supply

lab set

up. 0603 chip resistor pads are provided on the

bottom side of the evaluation board to terminate the ECL
driver (More information on termination is provided in
AN8020).  Solder the chip resistors to the bottom side of the
board on the appropriate input of the device pins labeled R1,
R2, R3, R4, R6, and R7, depending on the specific device.

Installing the SMA Connectors

Each configuration indicates the number of SMA

connectors needed to populate an evaluation board for a
given configuration. Each input and output requires one
SMA connector. Attach all the required SMA connectors
onto the board and solder the connectors to the board. Please
note that alignment of the signal connector pin of the SMA
can influence the lab results. The reflection and launch of the
signals are largely influenced by imperfect alignment and
soldering of the SMA connector.

Validating the Assembled Board

After assembling the evaluation board, it is recommended

to perform continuity checks on all soldered areas before
commencing with the evaluation process. Time Domain
Reflectometry (TDR) is another highly recommended
validation test.

Summary of Contents for ECLSOIC8EVB

Page 1: ...e used in conjunction with the device data sheet which contains full technical details on the device specifications and operation Board Lay Up The 8 lead SOIC evaluation board is implemented in four l...

Page 2: ...rent configurations The input output and power pin layout of the evaluation board is shown in Figure 3 The evaluation board has at least eleven possible configurable options Table 1 list the devices a...

Page 3: ...32D See Figure 7 4 MC100LVEL33D See Figure 7 4 MC100LVEL51D See Figure 4 1 MC100LVEL58D See Figure 8 5 MC100LVELT22D See Figure 11 8 MC100LVELT23D See Figure 12 9 ECLinPS PlusE Device Comments Configu...

Page 4: ...VEE and GND The VCC clip connects directly to pin 8 of the device The VEE clip connects directly to pin 5 of the device There are two GND clip footprints which can be connected to the ground plane of...

Page 5: ...Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4 MC10EL01D MC100EL01D Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes Yes MC10EL05D MC100EL05D MC10EL31D MC100EL31D MC10EL35D...

Page 6: ...Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4 MC10EL04D MC100EL04D No No Yes Yes Yes Yes No No Yes Yes Yes No Yes No Yes Yes MC10EL07D MC100EL0...

Page 7: ...ure 6 Configuration 3 Schematic R6 50 W Table 6 Configuration 3 Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Device J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4 MC10EL11D MC100EL11D Yes No Yes N...

Page 8: ...in 8 Optional Figure 7 Configuration 4 Schematic R2 50 W R1 50 W Table 7 Configuration 4 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4 MC10EL32...

Page 9: ...gure 8 Configuration 5 Schematic R3 50 W R2 50 W Table 8 Configuration 5 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J7 R7 C1 C4 MC100EP16VCD No No Yes Y...

Page 10: ...3 Pin 2 Pin 1 Pin 5 Pin 6 Pin 7 Pin 8 Figure 9 Configuration 6 Translator Schematic Table 9 Configuration 6 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J...

Page 11: ...Figure 10 Configuration 7 Translator Schematic Unloaded Testing Condition R2 50 W Table 10 Configuration 7 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6 J...

Page 12: ...in 6 Pin 7 Pin 8 Figure 11 Configuration 8 Translator Schematic J6 J4 J1 R7 50 W optional Table 11 Configuration 8 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3...

Page 13: ...iguration 9 Translator Schematic Unloaded Testing Condition R1 50 W R2 50 W R3 50 W R4 50 W Table 12 Configuration 9 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C...

Page 14: ...Figure 13 Configuration 10 Translator Schematic Unloaded Testing Condition R3 50 W Table 13 Configuration 10 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3 R3 J4 R4 C2 C3 J6 R6...

Page 15: ...2 Pin 1 Pin 5 Pin 6 Pin 7 Pin 8 J6 Figure 14 Configuration 11 Translator Schematic J2 J3 R1 50 W R2 50 W Table 14 Configuration 11 Device Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 J1 R1 J2 R2 J3...

Page 16: ...ignals VTT VCC 2 0 V in split power supply setup VTT is the system ground VCC is 2 0 V and VEE is 3 0 V or 1 3 V see Table 15 Table 15 Power Supply Levels Power Supply VCC VEE GND 5 0 V 2 0 V 3 0 V 0...

Page 17: ...Miniature Test Point 5015 http www keyelco com SMT Compact Test Point 5016 Thru Hole Mount Compact Test Point 5005 5009 Chip Capacitor AVC Corporation 0603 0 01 mF 10 06035C103KAT2A http www avxcorp c...

Page 18: ...fied 1 Connect a SMA connector on J1 2 Remove the 50 W chip resistor from R3 MC100EP16VSD This device has an option of varying the output swing amplitude and being driven single endedly In order to ut...

Page 19: ...Gerber Files Top Layer Second Layer VEE and Ground Plane Third Layer VCC and Ground Plane Figure 16 Gerber Files Bottom Layer ECLinPS ECLinPS Lite ECLinPS Plus and ECLinPS MAX are trademarks of Semic...

Page 20: ...ems or any FDA Class 3 medical devices or medical devices with a similar or equivalent classification in a foreign jurisdiction or any devices intended for implantation in the human body Should you pu...

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