34
Service Request Enable Register (SRE)
Enables or disables the bits of the STB. Cleared when power is
reset. Setting bits to 0 disables them in the STB. Setting the bits to 1
enables them. Bit assignments for the SRE and the STB are shown
below.
7
6
5
4
3
2
1
0
0
MSS
ESB
0
EAV
0
0
0
MSS
Master Summary Status. Set to 1 when ESB or EAV are 1
(enabled). Read using the *STB? command.
ESB
Set to 1 when at least one bit in ESR is 1.
EAV
Error Available. An error has been entered into the error
queue, and may be read using the Fault? command.
Event Status Register (ESR)
A two-byte register, in which the lower bits represent conditions of
the Calibrator. Cleared when read and when power is reset.
Event Status Enable Register (ESE)
Enables and disables bits in the ESR. Setting a bit to 1 enables the
corresponding bit in the ESR, and setting it to 0 disables the
corresponding bit. Cleared at power reset. Bit assignments for the
ESR and the ESE respectively are shown below.
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PON
0
CME
EXE
DDE
QYE
0
OPC
Summary of Contents for PCL1200
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