Omega PCI-DAS1602/16, User Manual, Page: 22 / 39

Via SW after
INDX_GT=1
# Post-Trigger Samples < 1/2 FIFO
Pre-Trigger Mode
Via SW after XTRIG has
been detected
(INDX_GT=1)
1 1
ADHF
# Post-Trigger Samples >1 FIFO
Pre-Trigger Mode
----------------------------------
1/2 FIFO < # Post-Trigger Samples < 1 FIFO
Pre-Trigger Mode
Via SW when remaining
count <1 FIFO
------------------------
Via SW after XTRIG has
been detected
(INDX_GT=1)
0 1
ADC Pacer
# Samples <1/2 FIFO
Normal Mode
Via SW immediately
1 0
ADHF
# Samples >1 FIFO
Normal Mode
----------------------------------
1/2 FIFO < # Samples < 1 FIFO
Normal Mode
Via SW when remaining
count <1 FIFO
------------------------
Via SW immediately
0 0
Sample CTR
Starts on...
FIFO Mode ARM is set... FFM0 PRTRG
C0SRC
This bit allows the user to select the clock source for user Counter 0.
1 = Internal 10MHz oscillator
0 = External clock source input via CTR0CLK pin on 100p connector.
READ
- - - - - - - XTRIG - - - - INDX-GT - - -
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
XTRIG
1 = External Trigger flip-flop has been set. This bit is write-cleared.
0 = External Trigger flip-flop reset. No trigger has been received.
INDX-GT
1 = Pre Trigger index counter has completed its count
0 = Pre Trigger index counter has not yet been gated on, or has not yet completed its count.
8.2.4 Calibration Register
BADR1 + 6
This register controls all autocal operations. A Write only register.
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