Omega PCI-DAS1602/16, User Manual, Page: 14 / 39

8.0 PCI-DAS1602/16 Register Description
The PCI-DAS1602/16 operation registers are mapped into the PC I/O address space. Unlike its
ISA counterpart, this board has several base addresses each corresponding to a reserved block of
addresses in I/O space. Of six Base Address Regions (BADR) available in the PCI 2.1 specifica-
tion, five are implemented in this design and are summarized as follows:
16-Bit WORD DAC Data, FIFO Clear Registers BADR4
8-Bit BYTE Pacer, Counter/Timer and DIO Registers BADR3
16-Bit WORD ADC Data, FIFO Clear Registers BADR2
16-Bit WORD General Control/Status Registers BADR1
32-Bit DWORD PCI Controller Operation Registers BADR0
Operations Function I/O Region
BADRn will likely be different on different machines. Assigned by the PCI BIOS, these Base
Address values cannot be guaranteed to be the same even on subsequent power-on cycles of the
same machine. All software must interrogate BADR0 at run-time with a READ_CONFIGURA-
TION_DWORD instruction to determine the BADRn values.
Please see the "AMCC S5933 PCI Controller Data Book, Spring 1996" for more information.
8.1 BADR0
BADR0 is reserved for the AMCC S5933 PCI Controller operations. This region supports 32-bit
DWORD operations
8.2 BADR1
The I/O region defined by BADR1 contains 5 control and status registers for ADC, DAC, inter-
rupt and Autocal operations. This region supports 16-bit WORD operations.
8.2.1 Interrupt / ADC FIFO Register
BADR1+ 0
Interrupt Control, ADC status. A read/write register.
WRITE
INT0 INT1 INTE DAHFIE EOAIE DAHFCL EOACL INTCL - - - - DAEMIE ADFLCL DAEMCL -
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Write operations to this register allow the user to select interrupt sources, enable interrupts, clear
interrupts as well as ADC FIFO flags. The following is a description of the Interrupt/ADC FIFO
Register:
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