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13-11

ML63326 User's Manual

Chapter 13  Voice Synthesis

13

13.6  Operation of the Voice Synthesis Section

The voice synthesis section has the functions of voice, melody, and buzzer outputs.

13.6.1  Description of Pins Related to Voice Synthesis

The DACOUT pin is the output pin of the 12-bit D/A converter, and the AOUT pin is the output
pin of the amplifier whose input is the output of the 12-bit D/A converter.  Both these pins are
used for the output of voice as well as melody/buzzer sounds.

At a system reset, the DACOUT pin will be at the AV

DD

 level and the AOUT pin will be at the

V

SS

 level.

The SPEN pin is the enable input pin for the amplifier which is intended for driving a
piezoelectric speaker.  When not using this amplifier, leave this SPEN pin open or tie it to
GND.  When using this amplifier, setting this pin to a "H" level only when the output is being
made will reduce the supply current.

The SPIN pin is the input pin for the amplifier which is intended for driving a piezoelectric
speaker.  Connect this pin to GND when this amplifier is not used.

The SP(–) pin is the negative side output pin for driving a piezoelectric speaker, and the SP(+)
pin is the positive side output pin.  Both pins will be at the V

SS

 level at a system reset.

The MD/MDB pins are used for outputting the melody/buzzer output of the voice synthesis
section or of the microcontroller section.  At a system reset, both these outputs will be at a
"L" level, and when the melody/buzzer output state is entered, the MDB pin outputs the
opposite level of the MD pin.

The BUSYB pin normally outputs a "H" level (V

DD

). It outputs a "L" level (0 V) when the voice

synthesis section is in the output state.

The ENVOICE pin is the pin that outputs the level of PC1 (bit 1 of PCD), and is used for the
RESET signal of the voice synthesis section.  This pin will be at a "L" level at a system reset
thereby putting the voice synthesis section in the reset state, and the voice synthesis section
goes into the enabled state when this pin is set to a "H" level (V

DD

).

The V

REF

 pin is the volume control function input pin that changes the amplitude of the output

at DACOUT.  When this pin is in the open condition, the 1/5 AV

DD

 voltage appears at this pin.

Leave this pin open when not using the volume control function.

Summary of Contents for ML63326

Page 1: ...ML63326 User s Manual CMOS 4 bit microcontroller SECOND EDITION ISSUE DATE Sep 1999 PEUL63326 02 Preliminary ...

Page 2: ...s granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof 6 The products listed in this document are intended for use in general electronics equipment for commercial applications e g office automation communication equipment mea...

Page 3: ......

Page 4: ...uals related to the ML63326 are shown below nX 4 250 Core Instruction Manual Describes the base architecture and instruction set of nX 4 250 core SASM63K User s Manual Describes the structured assembler operation and assembler language specifica tion Dr 63326 User s Manual Describes the hardware of the emulator DT63K Debugger User s Manual Describes the debugger commands This document is subject t...

Page 5: ...bytes n Symbol Note Gives more information about mistakable items n Terminology H level Indicates high side voltage signal levels VIH and VOH as specified by the electrical characteristics L level Indicates low side voltage signal levels VIL and VOL as specified by the electrical characteristics n Register description Invalid bit When read a value of 1 is always obtained Write operations are inval...

Page 6: ... CPU and Memory Spaces 2 1 Overview 2 1 2 2 Registers 2 1 2 2 1 Accumulator A 2 1 2 2 2 Flag Register 2 1 2 2 2 1 Carry Flag C 2 1 2 2 2 2 Zero Flag Z 2 2 2 2 2 3 G Flag G 2 2 2 2 3 Master Interrupt Enable Flag MIE 2 2 2 2 4 Current Bank Register CBR Extra Bank Register EBR HL Register HL XY Register XY 2 3 2 2 5 Program Counter PC 2 4 2 2 6 RA Registers RA3 RA2 RA1 RA0 2 4 2 2 7 Stack Pointer SP ...

Page 7: ...26 4 1 Overview 4 1 4 2 Interrupt Registers 4 3 4 3 Interrupt Sequence 4 10 4 3 1 Interrupt Processing 4 10 4 3 2 Return from an Interrupt Routine 4 11 4 3 3 Interrupt Hold Instructions 4 11 Chapter 5 Clock Generator Circuit OSC 5 1 Overview 5 1 5 2 Clock Generator Circuit Configuration 5 1 5 3 Low Speed Clock Generator Circuit 5 2 5 4 High Speed Clock Generator Circuit 5 4 5 5 System Clock Contro...

Page 8: ...7 15 7 4 5 Auto Reload Mode Operation 7 16 7 4 6 Capture Mode Operation 7 18 7 4 7 Frequency Measurement Mode Operation 7 21 Chapter 8 100 Hz Timer Counter 100HzTC 8 1 Overview 8 1 8 2 100 Hz Timer Counter Configuration 8 1 8 3 100 Hz Timer Counter Registers 8 2 8 4 100 Hz Timer Counter Operation 8 3 Chapter 9 Watchdog Timer WDT 9 1 Overview 9 1 9 2 Watchdog Timer Configuration 9 1 9 3 Watchdog Ti...

Page 9: ...ternal Interrupt 2 10 34 10 8 Port F PF 0 PF 3 10 35 10 8 1 Port F Configuration 10 35 10 8 2 Port F Registers 10 36 10 8 3 Port F External Interrupt Function External Interrupt 3 10 40 Chapter 11 External Memory Transfer Function EXTMEM 11 1 Overview 11 1 11 2 Connection with the External Memory 11 2 11 3 External Memory Address Space 11 3 11 4 Setting of Secondary Port Functions 11 4 11 5 Distin...

Page 10: ...g of Voice Output 13 13 13 7 3 Voice Output Procedure 13 14 13 8 Voice Output Duration 13 17 13 9 Melody 13 18 13 9 1 Tempo Data 13 18 13 9 2 Melody Data 13 20 13 9 3 Melody Circuit Application Example 13 24 13 9 4 Melody Output Procedure 13 25 13 10 Buzzer 13 27 13 10 1 Buzzer Output Procedure 13 28 13 11 Example of Connections Made for Extending the Voice Data Area 13 29 13 12 Example of Connect...

Page 11: ...Circuit POWER 17 1 Overview 17 1 17 2 Power Supply Circuit Configuration 17 1 17 3 Power Supply Circuit Operation 17 2 Appendixes Appendix A List of Special Function Registers Appendix 1 Appendix B Package Dimensions Appendix 13 Appendix C Input Output Circuit Configuration Appendix 14 Appendix D Peripheral Circuit Examples Appendix 16 Appendix E Electrical Characteristics Appendix 21 Appendix F I...

Page 12: ...imers TIMER 8 Chapter 8 100 Hz Timer Counter 100HzTC 9 Chapter 9 Watchdog Timer WDT 10 Chapter 10 Ports INPUT OUTPUT I O PORT 14 Chapter 14 Shift Register SFT 15 Chapter 15 LCD Driver LCD 17 Chapter 17 Power Supply Circuit POWER Appendixes 11 Chapter 11 External Memory Transfer Function EXTMEM 12 Chapter 12 Melody Driver MELODY63K 13 Chapter 13 Voice Synthesis 16 Chapter 16 Battery Low Detect Circ...

Page 13: ......

Page 14: ...Chapter 1 Overview 1 ...

Page 15: ......

Page 16: ...operations compare logic operations mask operations bit operations ROM table reference external memory transfer stack operations flag operations jump conditional branch call return control b Wide variety of addressing modes Indirect addressing mode for 4 types of data memory with current bank register extra bank register HL register and XY register Data memory bank internal direct addressing mode ...

Page 17: ...ports Input port Output ports I O ports 1 port 4 bits 4 ports 4 bits 5 ports 4 bits 1 port 2 bits j Voice synthesis section Algorithm 4 bit ADPCM method non linear 8 bit PCM method straight 8 bit PCM method Voice synthesis data area Internal ROM 1 Mbit mask ROM 128 Kbytes Stores voice data and character data etc External ROM 4 Mbit ROM 512 Kbytes max Sampling frequencies With a source oscillator o...

Page 18: ... 1 0 2 20 0 10 Ta 25 C 0 1 2 40 0 10 Ta 25 C 1 1 k Melody output MELODY63K Melody frequency 529 Hz to 2979 Hz Tone length 63 varieties Tempo 15 varieties Melody data Stored in program memory Buzzer driver signal output 4 kHz l LCD driver Number of segments 1024 segments max 64 seg 16 com 1 1 to 1 16 duty 1 4 or 1 5 bias internal regulator Selectable as all ON mode all OFF mode power down mode and ...

Page 19: ...Package Product Chip 159 pads ML63326 xxx 176 pin flat package 176LQFP ML63326 xxxTC LQFP176 P 2424 0 50 BK xxx indicates the ROM code number s Operating temperature 20 to 70 C t Power supply voltage 2 0 to 5 5 V 30 kHz to 2 048 MHz operating frequency internal clock ...

Page 20: ...TIMER l Æ7 1 100 Hz timer counter 100HzTC l Æ8 1 Watchdog timer WDT l Æ9 1 Input port INPUT PORT 1 port 4 bits P0 l Æ10 2 I O port I O PORT 5 ports 4 bits P9 l Æ10 15 PA l PB l Æ10 24 PE l Æ10 30 Melody driver MELODY63K l Æ12 1 Shift register SFT l Æ14 1 LCD driver LCD 16 lines Æ15 1 64 lines Display register 4 bits DSPR 256 Æ15 4 Bias generator BIAS l Æ15 6 Battery low detect circuit BLD l Æ16 1 ...

Page 21: ... TST2 INT WDT 1 VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDL BIAS INT326 ROM 24K 16bits BUS CON TROL MIE CBR EBR L C G Z ALU RA A IR INSTRUCTION DECODER nX 4 250 PC H Y X TIMING CON TROL SP RSP STACK CAL S 16 levels REG S 16 levels EXTMEM D0 D7 A0 A15 RD WR OUTPUT PORT PA 0 PA 3 PB 0 PB 3 PE 0 PE 3 P4 0 P4 3 P5 0 P5 3 P6 0 P6 3 P7 0 P7 3 P8 0 P8 1 PF 0 PF 3 SOUT SIN MELODY63K INT 1 VTEST OSCH XT1 OSC0 OSC1...

Page 22: ...16 SEG17 SEG18 SEG19 SEG20 SEG21 NC NC NC NC SEG22 SEG23 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 38 39 40 41 SEG58 SEG59 SEG60 SEG61 42 43 44 SEG62 SEG63 NC OSC0 OSC1 VDDL VDD CB2 CB1 VDDH C2 C1 VDD5 VDD4 VDD3 VDD2 VDD1 VSS COM16 COM15 COM14 COM13 COM12 88 87 86 85 ...

Page 23: ...19 100 V DD SEG1 18 101 V DDL SEG0 17 102 OSC1 COM8 16 103 OSC0 COM7 15 104 RESET COM6 14 105 XT1 COM5 13 106 XT0 COM4 12 107 TST1 COM3 11 108 TST2 COM2 10 109 VTEST COM1 9 110 BUSYB 111 ENVOICE 112 SPEN 113 V DDI 114 PF 3 115 PF 2 116 PF 1 117 PF 0 118 PE 3 V DD 8 AV DD 7 V REF 6 AOUT 5 SPIN 4 SP 3 SP 2 DACOUT 1 51 SEG34 P4 3 148 52 SEG35 P5 0 147 53 SEG36 P5 1 146 54 SEG37 P5 2 145 55 SEG38 P5 3...

Page 24: ...3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 2897 2757 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 ...

Page 25: ...9 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 3039 2772 2632 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 PE 0 PB 3 PB 2 PB 1 PB 0 PA 3 PA 2 PA 1 PA 0 P9 3 P9 2 P9...

Page 26: ...d VSS Power supply pin for the high speed clock generator circuit Connect a capacitor 1 0 mF between pin and VSS Capacitor connection pins for VDDH generation Connect a capacitor 1 0 mF between CB1 and CB2 Low speed clock oscillation pins Crystal oscillation or RC oscillation is selected by the mask option If crystal oscillation is selected connect a crystal between XT0 and XT1 and connect capacit...

Page 27: ...tor pin 110 O 77 ENVOICE Voice synthesis section enable monitor pin 111 O 78 Voice 127 126 125 124 4 bit output port Each bit can be selected as the following P channel open drain output N channel open drain output CMOS output High impedance output P4 0 A0 151 123 P4 1 A1 150 122 P4 2 A2 149 121 P4 3 A3 148 120 O P5 0 A4 147 119 P5 1 A5 146 118 P5 2 A6 145 117 P5 3 A7 144 116 O P6 0 A8 143 115 P6 ...

Page 28: ...be selected as the following Input with pull up resistor Input with pull down resistor High impedance input During the output mode each bit can be selected as the following P channel open drain output N channel open drain output CMOS output High impedance output P9 1 P9 2 P9 3 PA 0 I O PA 1 PA 2 PA 3 PB 0 INT0 TM0CAP TM0OVF I O PB 1 INT0 TM1CAP TM1OVF PB 2 INT0 T02CK PB 3 INT0 T13CK 97 96 95 94 13...

Page 29: ...M12 COM13 COM14 COM15 COM16 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 LCD O O 9 144 10 145 11 146 12 147 13 148 14 149 15 150 16 151 81 48 82 49 83 50 84 51 85 52 86 53 87 54 88 55 17 152 18 153 19 154 20 155 21 156 22 157 23 158 24 159 25 160 26 161 27 162 28 163 29 164 30 165 SEG26 SEG25 42 5 43 6 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 3...

Page 30: ...8 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 44 7 45 8 46 9 47 10 48 11 49 12 50 13 51 14 52 15 53 16 54 17 55 18 56 19 57 20 58 21 59 22 60 23 61 24 62 25 63 26 64 27 65 28 66 29 67 30 68 31 69 32 70 33 71 34 Pad No Pin No LCD segment signal output pins SEG27 to SEG63 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 72 35 73 36 74 37 75 38 76 39 77 40 78 41 79 42 80 43 Table 1 3 Pin Description Bas...

Page 31: ...P0 3 INT5 PB 0 TM0CAP Capture I Timer 0 capture trigger input pin PB 1 TM1CAP I Timer 1 capture trigger input pin PB 0 TM0OVF Timer O Timer 0 overflow flag output pin PB 1 TM1OVF O Timer 1 overflow flag output pin PB 2 T02CK I Timer 0 timer 2 external clock input pin PB 3 T13CK I Timer 1 timer 3 external clock input pin PE 0 SIN Shift register I Shift register receive data input pin PE 1 SOUT O Sh...

Page 32: ... Pad No P5 2 A6 P5 3 A7 P6 0 A8 P6 1 A9 145 144 143 142 117 116 115 114 113 112 111 110 P5 0 A4 119 147 P5 1 A5 118 146 P7 2 A14 137 109 P7 3 A15 136 108 P9 0 D0 133 105 P9 1 D1 132 104 P9 2 D2 131 103 P9 3 D3 130 102 PA 0 D4 129 101 PA 1 D5 128 100 PA 2 D6 127 99 PA 3 D7 126 98 I O P9 PA secondary functions Data bus signals for external memory access P8 0 secondary function Read signal negative l...

Page 33: ...ct TST1 and TST2 to VSS 3 Connect a capacitor 0 1 mF between the VDD2 pin and the VSS pin when the LCD drivers are not used 1 6 3 Unused Pin Processing Table 1 5 lists the handling of unused pins Table 1 5 Unused Pin Handling Pin Recommended pin handling OSC0 OSC1 Open CB1 CB2 Open TST1 TST2 VTEST Open or VSS P0 0 P0 3 Open P9 0 P9 3 Open PA 0 PA 3 Open PB 0 PB 3 Open PE 0 PE 3 Open MD MDB Open CO...

Page 34: ...ons are classified according to the number of machine cycles 1 machinecycleinstructions M1 2machinecycleinstructions M1 M2 and3machinecycle instructions M1 M2 M3 Most instructions are executed in 1 machine cycle 1 7 2 Port I O Basic Timing Figure 1 5 shows the basic I O timing During the execution of an instruction that outputs data to a port setting data data A is output at the rising edge of the...

Page 35: ...ptured in the internal register only if a H level is maintained w of Figure 1 6 throughout the data capture interval Therefore if noise occurs in the input data implement noise reduction measures with the program and peripheral devices MOV obj data A Output instruction Input instruction CLK Instruction example S1 S2 S1 S2 Output pin Input pin data B Accumulator data B data A MOV A obj Input instru...

Page 36: ...actor is sampled at the falling edge of CLK and an interrupt request IRQ is set at the first half of S1 When an interrupt condition is established and the CPU receives an interrupt the interrupt routine will start beginning from the next machine cycle Figure 1 7 Interrupt Basic Timing M1 M2 CLK Interrupt factor S1 S2 S1 S2 S1 S2 IRQ Process Main routine PC 1st interrupt address Interrupt routine ...

Page 37: ...1 22 ML63326 User s Manual Chapter 1 Overview ...

Page 38: ...Chapter 2 CPU and Memory Spaces 2 ...

Page 39: ......

Page 40: ...processes data mainly with the accumulator and register set The register set is a programming model consisting of the HL and XY registers that store data memory addresses the current bank register CBR the extra bank register EBR the RA register that stores program memory addresses registers that control program flow and registers that control flags and memory 2 2 1 Accumulator A The accumulator A ...

Page 41: ...Interrupt Enable Flag MIE MIE bit0ofMIEF isaflagthatdisablesorenablesallinterruptsexceptforthewatchdogtimer interrupt MIEF is a 4 bit register in which bit 0 is the master interrupt enable flag MIE If MIE is 0 all interrupts are disabled If MIE is 1 all interrupts are enabled with the exception of the watchdog timer When any interrupt is received MIE is cleared to 0 MIE is set to 1 by execution of...

Page 42: ...igure 2 1 Various Register Combinations A11 to A0 in Figure 2 1 indicate data memory addresses 4K nibbles max At system reset the CBR EBR HL and XY registers are initialized to 0 When an interrupt occurs a PUSH HL or PUSH XY instruction can be used if necessary to save the CBR EBR HL and XY registers on the register stack These registers can be restored with a POP HL or POP XY instruction The CBR ...

Page 43: ...truction that uses RA registers do not use addresses located in the SFR area to transfer ROM table data to RA registers otherwise indirect addressing of program memory will not operate properly RA3 RA2 RA1 RA0 A15 A12 A11 A8 A7 A4 A3 A0 Figure 2 2 Address Configuration of RA3 to RA0 Registers Within the A15 to A0 of Figure 2 2 A14 to A0 indicate program memory addresses 32K words max RA3 to RA0 ar...

Page 44: ...ress 0FH Because the hardware requires 1 level of the call stack during program execution only 15 levels can be used for stack saves The contents of the call stack cannot be read or written by the program Figure 2 3 shows the relation between SP and the call stack 3 2 1 0 SP Stack pointer Call stack 0FH 16 levels 0H 15 bits Figure 2 3 Relation Between SP and Call Stack SP is assigned to special fu...

Page 45: ...tween RSP and the register stack 2 1 0 RSP Register stack pointer Register stack 0FH 16 levels 0H 16 bits 3 Figure 2 4 Relation Between RSP and Register Stack The various registers shown in Figure 2 5 are saved onto and restored from the register stack by PUSH and POP instructions At system reset RSP is initialized to 0 and points to address 0H of the register stack rsp3 rsp2 rsp1 rsp0 RSP 0F6H bi...

Page 46: ... Figure 2 6 Program Memory Space Configuration After system reset instruction execution begins at address 0000H The interrupt area from address 0010H to address 0037H contains starting addresses of the interrupt processing routines that are executed when interrupts are generated Refer to Chapter 4 Interrupt ROM table data is transferred to data memory by ROM table reference instructions The melody...

Page 47: ...BANK 0 is allocated as a SFR area BANK 1 as the LCD display register and BANK 2 and the following BANKS are data RAM Figure 2 7 shows the configuration of the data memory space BANK5 BANK2 BANK1 BANK0 7FFH 300H 2FFH 200H 1FFH 100H 0FFH 000H Data RAM area 1536 nibbles Display register 256 nibbles SFR area 256 nibbles BANK3 400H 3FFH 500H 4FFH BANK4 600H 5FFH 700H 6FFH BANK6 BANK7 Figure 2 7 Data Me...

Page 48: ...thesis and Character Data The memory space for voice synthesis and character data is configured by a mask ROM that storesthevoicedatanecessaryforthebuilt invoicesynthesisfunctionandthecharacterdata used for the LCD display Figure 2 8 Memory Space Configuration 1FFFFH 0000H 131 072 bytes 8 bits ...

Page 49: ...memory space is one for storing the voice data necessary for the built in voice synthesisfunctionandthecharacterdatausedfortheLCDdisplay andisaccessedviaaport The external memory space configuration is shown in Figure 2 9 Figure 2 9 External Memory Space Configuration 7FFFFH 0000H 524 288 bytes 8 bits ...

Page 50: ...CPU Control Functions Chapter 3 3 ...

Page 51: ......

Page 52: ...t processing where registers and pins are initialized The CPU remains in this state until instruction execution begins After system reset processing instruction execution begins from address 0000H The halt mode is the state in which the CPU is halted instruction execution suspended but internal peripheral functions continue to operate During the halt mode the PC is not incremented Evenuponentering...

Page 53: ...ay registers are not initialized After system reset processing instruction execution begins from address 0000H Figures 3 2 and 3 3 show the system reset generator circuit and signals when a system reset is generated Figure 3 3 Signals When System Reset is Generated Note System reset takes priority over all other processing and terminates all processing up to that point in time Therefore the conten...

Page 54: ... the interrupt routine is entered When an RTI instruction is used to complete the interrupt routine the main routine is resumed beginning from the instruction immediately following the HALT instruction Figure 3 4 shows the timing when a HALT instruction and interrupt request occur simultane ously S1 S2 S1 S2 S1 S2 S2 S1 S2 S1 S2 S1 S2 S1 S2 HALT HALT instruction execution RTI instruction execution...

Page 55: ...ered When an RTI instruction is used to complete the interrupt routine the main routine is resumed beginning from the second instruction after the HALT instruction Figure 3 5 Timing of Transfer to Halt Mode and Release of Halt Mode by Interrupt Note If the halt mode is to be released set individual interrupt enable flags to 1 If an individual interrupt enable flag is 0 the corresponding interrupt ...

Page 56: ...ircuit and the HALT instruction is executed again This sequence is indicated in Figure 3 6 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S2 S2 S2 HALT HALT instruction execution n HLT halt flag Melody data request PC flow in main routine HALT instruction address Melody data address Halt mode Halt mode HALT Melody data transfer HALT instruction execution melody Execution of instruction immediately after HALT...

Page 57: ...3 6 ML63326 User s Manual Chapter 3 CPU Control Functions ...

Page 58: ...Interrupt INT326 Chapter 4 4 ...

Page 59: ......

Page 60: ...10H 2 Melody end interrupt MDINT 0012H 3 External interrupt 0 PB 4 bit OR input XI0INT 0014H 5 External interrupt 2 PE 3 XI2INT 0018H 7 8 9 Timer 0 interrupt TM0INT 0020H 10 Timer 1 interrupt TM1INT 0022H 11 Timer 2 interrupt TM2INT 0024H 12 Timer 3 interrupt TM3INT 0026H 13 Shift register interrupt SFTINT 002CH 14 15 T10 Hz interrupt T10HzINT 002EH 16 32 Hz interrupt 32HzINT 0030H 16 Hz interrupt...

Page 61: ...0 IRQ2 2 QTM2 IRQ2 1 QTM1 IRQ2 3 QTM3 IRQ2 TM0INT TM1INT TM2INT TM3INT IE2 0 ETM0 IE2 1 ETM1 IE2 2 ETM2 IE2 3 ETM3 IE2 IRQ3 2 QSFT IRQ3 3 Q10Hz IRQ3 SFTINT T10HzINT IE3 2 ESFT IE3 3 E10Hz IE3 IRQ4 0 Q32Hz IRQ4 2 Q4Hz IRQ4 1 Q16Hz IRQ4 3 Q2Hz IRQ4 32HzINT 16HzINT 4HzINT 2HzINT IE4 0 E32Hz IE4 1 E16Hz IE4 2 E4Hz IE4 3 E2Hz IE4 Interrupt request Master interrupt enable flag IRQ1 3 QXI5 XI5INT IE1 3 E...

Page 62: ...terrupt If MIE is 0 all interrupts are disabled If MIE is 1 all interrupts are enabled with the exception of the watchdog timer When any interrupt is received MIE is cleared to 0 MIE is set to 1 by execution of a return from interrupt instruction RTI instruction If multi level interrupt processing is to be performed execute a RTI instruction MIE 1 during the interrupt processing routines At system...

Page 63: ... are accepted in order of highest priority and low priority interrupts are placed on hold When an interrupt is received the master interrupt enable flag MIE is cleared to 0 The corresponding bits in the interrupt enable registers IE0 to IE4 do not change At system reset each bit of IE0 through IE4 is initialized to 0 EVI EXI0 EMD External interrupt 0 enable flag 0 Disable initial value 1 Enable bi...

Page 64: ... bit 2 bit 1 bit 0 4 Hz interrupt enable flag 0 Disable initial value 1 Enable 16 Hz interrupt enable flag 0 Disable initial value 1 Enable 32 Hz interrupt enable flag 0 Disable initial value 1 Enable IE4 054H R W ETM3 ETM2 ETM1 ETM0 Timer 3 interrupt enable flag 0 Disable initial value 1 Enable bit 3 bit 2 bit 1 bit 0 Timer 2 interrupt enable flag 0 Disable initial value 1 Enable Timer 1 interrup...

Page 65: ...ed the corresponding bits of IRQ0 to IRQ4 are cleared to 0 At system reset each bit of IRQ0 through IRQ4 is initialized to 0 bit 3 QVI reQuest Voice synthesis Interrupt This is the interrupt request signal from the voice synthesis section An interrupt request is generated when the setting of one voice phrase is completed and the setting of the next voice phrase is enabled by the voice synthesis se...

Page 66: ... as a secondary function to each bit PF 0 to PF 3 of port F An external interrupt 3 request is generated through the 4 bit ORed input bit 0 QXI2 reQuest eXternal Interrupt 2 External interrupt 2 request flag The external interrupt 2 is assigned as a secondary function of port E 3 PE 3 Generation of the external interrupt 2 is triggered by the falling edge of the 128 Hz or 4 kHz output of the time ...

Page 67: ...mer 3 interrupt request flag 0 No request initial value 1 Request bit 3 bit 2 bit 1 bit 0 Timer 2 interrupt request flag 0 No request initial value 1 Request Timer 1 interrupt request flag 0 No request initial value 1 Request Timer 0 interrupt request flag 0 No request initial value 1 Request IRQ2 057H R W bit 3 QTM3 reQuest TiMer 3 Timer 3 interrupt request flag A timer 3 interrupt request is gen...

Page 68: ...z interrupt request flag A 2 Hz interrupt request is generated at every falling edge of the 2 Hz output of the time base counter bit 2 Q4Hz reQuest 4 Hz 4 Hz interrupt request flag A 4 Hz interrupt request is generated at every falling edge of the 4 Hz output of the time base counter bit1 Q16Hz reQuest 16 Hz 16 Hz interrupt request flag A 16 Hz interrupt request is generated at every falling edge ...

Page 69: ...erformed when an interrupt is generated 1 MIE and the corresponding interrupt request flag are cleared to 0 2 The program counter PC is saved on the call stack 3 The call stack pointer SP is incremented by 1 SP SP 1 4 The starting address of the interrupt routine is loaded into the program counter PC Interrupt processing is performed in 0 machine cycles Figure 4 2 shows the stack contents after an...

Page 70: ...rupt is processedandan RTI instructionisexecuted theMIEflagwillbesetto 1 andinterrupts enabled Use RTNMI instructions to return from watchdog timer interrupts only Use RTI instructions for normal interrupts 4 3 3 Interrupt Hold Instructions Interrupt requests are not received during execution of the following instructions These instructions are processed with priority and interrupt processing is d...

Page 71: ...4 12 ML63326 User s Manual Chapter 4 Interrupt INT326 ...

Page 72: ...Clock Generator Circuit OSC Chapter 5 5 ...

Page 73: ......

Page 74: ...ck for the CPU The time base clock is the basic operation clock for the time base counter Depending on the contents of the frequency control register FCON the system clock frequency is switched to either the output of the low speed clock generator circuit TBCCLK or the output of the high speed clock generator circuit HSCLK The frequency control register FCON also controls modes of the high speed c...

Page 75: ...ch an external crystal unit and capacitor CG as shown in Figure 5 2 b Inside the IC Low speed clock output a External Circuit for RC Oscillation Mode XT0 XT1 ROSL VDD2 CXT VSS Inside the IC Low speed clock output b External Circuit for Crystal Oscillation Mode XT0 XT1 Crystal VDD2 Rf CG VSS VSS CD Figure 5 2 External Circuits for Low Speed Clock Oscillation Note For convenience the descriptions of...

Page 76: ...able 5 2 shows an example external component to be attached when the low speed side crystal oscillation mode is selected Table 5 1 Typical Oscillation Frequencies for the Low Speed Side RC Oscillation Mode Typ Table 5 2 Example External Component for the Low Speed Side Crystal Oscillation Mode ROSL 1 5 MW 700 kW 400 kW fROSL 32 kHz 30 60 kHz 30 80 kHz 30 CG 12 pF fXT 32 768 kHz ...

Page 77: ... waveform of the source oscillations is output as the high speed clock The maximum frequency of the source oscillations in this case is 4 096 MHz Ifthehigh speedclockisnottobeused leavetheOSC0andOSC1pinsopen unconnected For the RC oscillation mode attach an external resistor ROSH as shown in Figure 5 3 a For the crystal oscillation mode attach an external crystal unit and capacitors as shown in Fi...

Page 78: ...nku Corp ROSH VDDH fROSH 3 6 V 1 9 MHz 30 39 kW 4 2 V 2 1 MHz 30 4 8 V 2 2 MHz 30 3 6 V 1 6 MHz 30 47 kW 4 2 V 1 7 MHz 30 4 8 V 1 8 MHz 30 CL0 CL1 8 pF 8 pF Crystal unit AT 49 4 096 MHz Note The power supply voltage VDDH of the high speed clock generator circuit is a voltage obtained by doubling the voltage VDD2 used in the LCD bias generator section Take care because VDD2 can be varied from 1 8 V...

Page 79: ...he oscillating state ENOSC 1 The low speed generator circuit will continue to oscillate even when the high speed generator circuit is selected To reduce the total power consumption in applications that use the high speed clock generator circuit the following clock controls are generally implemented in software During normal operation the output of the low speed clock generator circuit CPUCLK 0 sho...

Page 80: ...alue 1 High speed clock oscillation output FCON 062H R W bit 3 bit 2 bit 1 bit 0 bit 2 OSCSEL This bit selects the RC oscillation mode or the crystal oscillation mode of the high speed clock generator circuit At system reset this bit is cleared to 0 selecting the RC oscillation mode bit 1 ENOSC This bit starts and stops oscillation of the high speed clock generator circuit At system reset this bit...

Page 81: ...ode ENOSC bit 1 of FCON 0 2 High speed clock oscillation stop ENOSC 0 Stop high speed clock oscillation initial value ENOSC 1 Start high speed clock oscillation Software processing Software processing ENOSC bit 1 of FCON 1 2 High speed clock oscillation start ENOSC 0 Stop high speed clock oscillation initial value ENOSC 1 Start high speed clock oscillation Wait When RC oscillation mode selected 5 ...

Page 82: ... 0 V Approx 1 7 V typ Low speed clock OSC1 Power supply voltage for high speed oscillation VDDH 2 VDD2 VSS 0 V Figure 5 4 System Clock Select Timing In the crystal oscillation mode 10 ms are required from the time when ENOSC is set to 1 until the high speed clock generator circuit enters the oscillating state Therefore in this mode when switching CPUCLK to a high speed setting wait for an interval...

Page 83: ...5 10 ML63326 User s Manual Chapter 5 Clock Generator Circuit OSC ...

Page 84: ...Time Base Counter TBC Chapter 6 6 ...

Page 85: ......

Page 86: ...6 2 Time Base Counter Configuration The configuration of the time base counter TBC is shown in Figure 6 1 b3 b2 b1 b0 b3 b2 b1 b0 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz 256 Hz 512 Hz 1 kHz 2 kHz 4 kHz 8 kHz 16 kHz 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz 256 Hz 512 Hz 1 kHz 2 kHz 4 kHz 8 kHz 16 kHz TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC11 TBC10 TBC9 TBC8 TBC15 TBC14 TBC13 TBC12 R R R TBC...

Page 87: ...ecial function registers SFRs are used to read the 1 to 8 Hz and 16 to 128 Hz outputs of the time base counter A write operation to TBCR0 sets both the 1 to 8 Hz and 16 to 128 Hz outputs to 0 and a write operation to TBCR1 sets the 1 to 8 Hz output to 0 16 Hz 32 Hz 64 Hz 128 Hz TBCR0 060H R W bit 3 bit 2 bit 1 bit 0 1 Hz 2 Hz 4 Hz 8 Hz TBCR1 061H R W bit 3 bit 2 bit 1 bit 0 ...

Page 88: ...TBCR0 TBCR1 A write operation to TBCR1 sets the 1 to 8 Hz output counter to 0 and a write operation to TBCR0 sets both the 1 to 8 Hz and 16 to 128 Hz output counters to 0 The write data in these write operations has no significance For example the MOV TBCR0 A instruction can be usedtowrite butisnotdependentonaccumulatorcontentinanyway Whenwriteisexecuted to TBCR0 and TBCR1 and the 1 to 8 Hz and 16...

Page 89: ... 6 Time Base Counter TBC Figure 6 2 Interrupt Timing and Reset Timing by Writing 1 to TBCR0 TBCR1 Write TBCR0 256 Hz 128 Hz 64 Hz 32 Hz 16 Hz Write TBCR1 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz 1 second 0 1 16 1 second 0 1 256 Shows interrupt timing ...

Page 90: ...Timers TIMER Chapter 7 7 ...

Page 91: ......

Page 92: ...s 1 and 3 respectively In addition to pulse generation and time measurement timers can also be used Figure 7 1 Timer 0 Configuration 7 2 Timer Configuration Figures 7 1 through 7 4 show the configuration of timers 0 to 3 Control circuit Frequency measurement control circuit Capture control circuit TM0CL TM0CH TM0DL TM0DH 8 8 Capture Reload 4 4 4 4 D Q D Q Q R TM0CK TM0 overflow TM0INT PB 0 TM0OVF ...

Page 93: ...1 overflow Figure 7 2 Timer 1 Configuration Control circuit Frequency measurement control circuit TM2CL TM2CH TM2DL TM2DH 8 Reload 4 4 4 4 D Q D Q Q R TM2CK TM2 overflow TM2INT TM2OVF Data bus TBCCLK HSCLK PB 2 T02CLK 64 Hz 437C TM2CK RESETS OV Figure 7 3 Timer 2 Configuration Control circuit TM3CL TM3CH TM3DL TM3DH 8 Reload 4 4 4 4 D Q Q R D Q TM3CK TM3INT TM3OVF Data bus TBCCLK HSCLK PB 3 T13CK ...

Page 94: ...e capture mode timer data registers store the capture data Writing to a timer data register causes the contents of the timer counter register to be transferred to the timer data register At system reset all valid bits are cleared to 0 Note regarding register values Writing to the timer counter register causes the same value to also be written to the timer data register However when writing to the ...

Page 95: ... 1 bit 0 2 Timer counter registers TM0CL TM0CH TM1CL TM1CH TM2CL TM2CH TM3CL TM3CH 8 bit binary counter operation At system reset all valid bits are cleared to 0 Note regarding register values Writing to the timer counter register causes the same value to also be written to the timer data register However when writing to the timer data register the same value is not written to the timer counter re...

Page 96: ... TM1CH Timer 1 upper bit 3 bit 2 bit 1 bit 0 Timer 2 Registers T2C3 T2C2 T2C1 T2C0 07AH R W TM2CL Timer 2 lower bit 3 bit 2 bit 1 bit 0 T2C7 T2C6 T2C5 T2C4 07BH R W TM2CH Timer 2 upper bit 3 bit 2 bit 1 bit 0 Timer 3 Registers T3C3 T3C2 T3C1 T3C0 07CH R W TM3CL Timer 3 lower bit 3 bit 2 bit 1 bit 0 T3C7 T3C6 T3C5 T3C4 07DH R W TM3CH Timer 3 upper bit 3 bit 2 bit 1 bit 0 ...

Page 97: ...e is not written to the timer counter register Timer 0 Registers To use timer 1 in combination as a 16 bit timer set timer 1 control registers TM1CON0 and TM1CON1 FMEAS0 TM0ECAP TM0RUN TM0CON0 070H R W bit 3 bit 2 bit 1 bit 0 Timer 0 mode select bit 2 0 0 0 0 1 1 1 1 bit 1 0 0 1 1 0 0 1 1 bit 0 0 1 0 1 0 1 0 1 Auto reload mode stop initial value Auto reload mode operation Capture mode stop Capture...

Page 98: ...t 1 0 TM0CL1 TM0CL0 These bits select the timer 0 clock The timer 0 clock can be selected as TBCCLK low speed clock HSCLK high speed clock or external clock T02CK secondary function of PB 2 Note If HSCLK is used as the clock after ENOSC bit 1 of FCON is set to 1 wait for the following time interval before starting timer operation Wait at least 10 ms when using crystal oscillation Wait at least 5 m...

Page 99: ...1 073H R W bit 3 bit 2 bit 1 bit 0 Timer 1 clock select bit 1 0 0 1 1 bit 0 0 1 0 1 TBCCLK initial value HSCLK External clock Timer 0 overflow 16 bit timer mode bit 1 0 TM1CL1 TM1CL0 These bits select the timer 1 clock The timer 1 clock can be selected as TBCCLK low speed clock HSCLK high speed clock external clock T13CK secondary function of PB 2 or the timer 0 overflow flag When using as a 16 bi...

Page 100: ...ration mode can be selected as auto reload mode or frequency measurement mode TM2CL1 TM2CL0 TM2CON1 07FH R W bit 3 bit 2 bit 1 bit 0 Timer 2 clock select bit 1 0 0 1 1 bit 0 0 1 0 1 TBCCLK initial value HSCLK External clock Not used bit 1 0 TM2CL1 TM2CL0 These bits select the timer 2 clock The timer 2 clock can be selected as TBCCLK low speed clock HSCLK high speed clock or external clock T02CK se...

Page 101: ... select bit 1 0 0 1 1 bit 0 0 1 0 1 TBCCLK initial value HSCLK External clock Timer 2 overflow 16 bit timer mode bit 1 0 TM3CL1 TM3CL0 These bits select the timer 3 clock The timer 3 clock can be selected as TBCCLK low speed clock HSCLK high speed clock external clock T13CK secondary function of PB 3 or the timer 2 overflow flag When using as a 16 bit timer select timer 2 overflow for the clock No...

Page 102: ...e the last time TM0CAP was read When TM0CAP 1 A value of 1 indicates that there is new capture data since system reset orsincethelasttimeTM0CAPwasread Additionalcapturesaredisabled At system reset TM0CAP is cleared to 0 In the capture mode if the level of the capture input pin PB 0 TM0CAP changes and a capture is generated TM0CAP is automatically set to 1 If TM0STAT is read TM0CAP is automatically...

Page 103: ...bit indicates that the timer counter register has overflowed This bit toggles between 0 and 1 whenever overflow occurs At system reset TM1OVF is cleared to 0 Timer 2 Register TM2OVF TM2STAT 082H R bit 3 bit 2 bit 1 bit 0 Timer 2 overflow flag 0 Initial value 1 Toggles between 0 and 1 each time the timer 2 counter register overflows bit 0 TM2OVF TiMer2 OVerFlow This bit indicates that the timer cou...

Page 104: ...H 0H Timer 1 control register 0 TM1CON0 072H 0CH Timer 1 control register 1 TM1CON1 073H 0CH Timer 1 status register TM1STAT 075H R 0CH R W R W Timer 2 Registers Name Symbol Address R W Initial value Timer 2 data register L TM2DL 076H R W 0H Timer 2 data register H TM2DH 077H 0H Timer 2 counter register L TM2CL 07AH 0H Timer 2 counter register H TM2CH 07BH 0H Timer 2 control register 0 TM2CON0 07E...

Page 105: ...an 1 cycle of the system clock CLK 7 4 2 Timer Data Registers TM0DL TM0DH TM1DL TM1DH TM2DL TM2DH TM3DL and TM3DH are 4 bit registers In the auto reload mode the timer data registers save values that are reloaded into the timer counter registers when the timer counter registers overflow In the capture mode the timer data registers save the value of the timer counter registers when a capture signal...

Page 106: ...register overflow Table 7 1 lists timer interrupts Timer clock TM0CH TM0CL TM0DH TM0DL TM0INT TM0OVF 10 FE FF 10 11 FF 10 11 Figure 7 5 Timer Counter Register Overflow Timing for Timer 0 Table 7 1 List of Timer Interrupts Interrupt factor Symbol IRQ flag IRQ2 IE flag IE2 Interrupt vector address Timer 0 interrupt TM0INT Timer 1 interrupt TM1INT Timer 2 interrupt TM2INT Timer 3 interrupt TM3INT ETM...

Page 107: ...ing begins from the value Setting the RUN bits TM0RUN TM1RUN TM2RUN TM3RUN for each timer control register to 1 will restart the count and resetting to 0 stops the count In the 16 bit timer mode for timers 0 and 1 the TM1RUN bit is disabled and start stop is controlled with the TM0RUN bit In the 16 bit timer mode for timers 2 and 3 the TM3RUN bit is disabled and start stop is controlled with the T...

Page 108: ...er continues to count up from BFFFH y Before the timer counter register overflows write the next reload value 534FH to the timer data register u When the timer counter register overflows 534FH is set to the timer counter register timer interrupt TM1INT is generated and timer 1 overflow flag TM1OVF toggles The timer counter register resumes counting from address 534FH i Repeat steps 4 through 7 Thi...

Page 109: ...r counter register overflows counting is restarted from 00H When a capture occurs the capture flags TM0CAP TM1CAP of the timer status registers TM0STAT TM1STAT aresetto 1 Additionalcapturesaredisabledwhilethecaptureflags are 1 The capture flags are assigned to bit 0 of the timer status registers and are automatically cleared to 0 when the timer status registers are read If both the TM1CL1 and TM1C...

Page 110: ...pture The high level pulse width t1 of the PB 0 input can be determined as follows t1 F0H 50H tCLK tCLK TMCLK cycle u TM0INT is generated when the timer counter register overflows When overflow occurs thetimercounterregisterchangesfromFFHto00Handcontinuesupward counting i If the PB 0 TM0CAP input changes repeat operations r and t third capture Because the counter overflows once during the interval...

Page 111: ... 7 Timers TIMER CAPT D Q D Q D Q PB 0 TM0CAP input Timer clock TM0ECAP TM0CAP Q Figure 7 10 Capture Signal CAPT Generator Circuit Note The maximum delay from a PB 0 TM0CAP input level change until capture is one cycle of the timer clock ...

Page 112: ... timer FFFF N1 TM3CH TM3CL TM2CH TM2CL TM3DH TM3DL TM2DH TM2DL 64 Hz 437C FMEAS2 437 32768 s H q Ø t Ø e w r 0000 Figure 7 11 Frequency Measurement Mode Timing The operation sequence for Figure 7 11 is as follows q Timer 3 control registers 0 and 1 TM3CON0 TM3CON1 are set for 16 bit timer mode and the timer counter and timer data register are cleared to 0 Enable the high speed clock by the frequen...

Page 113: ... means that the timer data register should be set to FF30H so that the counter overflows every 208 counts of the 2 MHz clock in auto reload mode As a result overflow produces a TM3INT cycle tTM3INT of tTM3INT 1 2000000 208 0 104 ms 9615 Hz In the same way assuming that RC oscillation clock is 600 kHz due to manufacturing variation we get N1 600000 437 32768 8001 decimal 1F41 hexadecimal 0001 1111 ...

Page 114: ...7 Figure 7 12 illustrates the operation of timer 3 interrupt for an RC oscillator clock frequency of 600 kHz H FFFF FFC2 TM3CH TM3CL TM2CH TM2CL 0000 TM3DH TM3DL TM2DH TM2DL TM3INT 9677 Hz FFC2 0 10333 ms Figure 7 12 Timer 3 Interrupt TM3INT Generation ...

Page 115: ...7 24 ML63326 User s Manual Chapter 7 Timers TIMER ...

Page 116: ...Chapter 8 8 100 Hz Timer Counter 100HzTC ...

Page 117: ......

Page 118: ...tput 512 Hz of the time base counter to generate a 10 Hz interrupt The 100 Hz timer consists of a 5 6 base counter and two decimal counters 8 2 100 Hz Timer Counter Configuration Figure 8 1 indicates the configuration of the 100 Hz timer counter 5 6 base counter decimal counter decimal counter 4 bit latch T10HzINT b3 b2 b1 b0 b3 b2 b1 b0 R R L Data bus T100CR READ T10CR READ T100CR WRITE T10CR WRI...

Page 119: ...d the 100 Hz counter of the 100 Hz timer counter The content of the T100CR is latched by a 4 bit latch in T10CR read operation so the value of the T100CR must always be read after reading T10CR When data is written in T100CR both T100CR and T10CR are reset to 0 bit 0 ECNT This bit controls count start stop for the 100 Hz timer counter internal counter Count starts when set to 1 At system reset the...

Page 120: ...t of that counter is input to the 10 Hz counter T10CR The 10HzINT signal which is the carry output 10 Hz of the T100CR 100 Hz counter also generates an interrupt request setting bit 3 Q10Hz of interrupt request registers 3 IRQ3 to 1 If either T100CR or T10CR is written to both are reset to 0 The write data used has no significance For example the MOV T100CR A instruction is not dependent on the co...

Page 121: ...8 4 ML63326 User s Manual Chapter 8 100 Hz Timer Counter 100HzTC ...

Page 122: ...Chapter 9 9 Watchdog Timer WDT ...

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Page 124: ...e time base counter TBC and a watchdog timer control register WDTCON to start and clear WDTC 9 2 Watchdog Timer Configuration Figure 9 1 shows the configuration of the watchdog timer 5H detection and latch 0AH detection 1 29 WDTC QWDACK internal reception signal RESETS system reset WDTINT interrupt request 256 Hz from time base counter Watchdog timer counter R Data bus 4 Internal pointer WDTCON WD...

Page 125: ...n WDTC overflows 1FFH 000H a watchdog timer interrupt request WDTINT is generated WDTINT cannot be disabled by the software non maskable interrupt and has the highest level of interrupt priority The WDTC overflow cycle T is given by 128 512 T 2 s 32768 Hz The minus deviation t of the WDTC overflow cycle is given by 128 t approximately 3 9 ms 32768 Hz Therefore the WDTC clear cycle Ct can be comput...

Page 126: ...N Write 0AH to WDTCON Write 5H to WDTCON Processing Write 0AH to WDTCON Processing WDT operation is stopped Internal pointer 0 WDT operation is started Internal pointer 1 Æ 0 Internal pointer 0 Æ 1 Processing time does not exceed 1 9961 s Internal pointer 0 Æ 1 WDTC is cleared Internal pointer 1 Æ 0 Figure 9 2 Watchdog Timer Processing Flowchart ...

Page 127: ...al pointer 0Æ1 e Write 0AH to WDTCON to start WDTC Internal pointer 1Æ0 r Write 5H to WDTCON Internal pointer 0Æ1 t Write 0AH to WDTCON to clear WDTC Internal pointer 1Æ0 y Write 5H to WDTCON Internal pointer 0Æ1 u After a fault occurs 5H is written to WDTCON but is not accepted since the internal pointer is 1 Internal pointer 1Æ0 i 0AH is written to WDTCON but since the internal pointer is 0 and ...

Page 128: ...Chapter 10 10 Ports INPUT OUTPUT I O PORT ...

Page 129: ......

Page 130: ...rt is to be connected to an external device that operates on a different power supply the power supply of the external device must be fed to the VDDI pin Note Since VDDI is separated from the positive power supply pin VDD power must be supplied to the VDDI pin 10 2 Ports List The ports of the ML63326 are shown in Table 10 1 Table 10 1 Ports List Port Interrupt Sedondary function Port 0 Port 9 Port...

Page 131: ...N0 P0CON1 4 4 VDDI 4 P0 0 P0 3 VSS Read P0D 4 4 P0 0 P0 3 to external interrupt 5 control circuit Data bus Figure 10 1 Input Only Port Port 0 Configuration 10 3 2 Port 0 Registers 1 Port 0 Data Register P0D The port 0 data register P0D is a 4 bit read only special function register SFR used to read the pin levels of each bit of port 0 P03 P02 P01 P00 P0D 000H R bit 3 bit 2 bit 1 bit 0 Pin levels o...

Page 132: ...ct 0 Input with pull up pull down resistor initial value 1 High impedance input Port 0 0 input mode select 0 Input with pull up pull down resistor initial value 1 High impedance input P0PUD P0F P0CON1 011H R W bit 3 bit 2 bit 1 bit 0 Port 0 pull up pull down resistor mode select 0 Inputs with pull down resistors initial value 1 Inputs with pull up resistors External interrupt sampling frequency se...

Page 133: ...eared to 0 and all bits of port 0 are initialized to the interrupt disabled state P03IE P02IE P01IE P00IE P0IE 012H R W bit 3 bit 2 bit 1 bit 0 Port 0 3 interrupt disable enable select 0 Interrupt disabled initial value 1 Interrupt enabled Port 0 2 interrupt disable enable select 0 Interrupt disabled initial value 1 Interrupt enabled Port 0 1 interrupt disable enable select 0 Interrupt disabled in...

Page 134: ...e port 0 inputs each bit of the port must be read to determine which bit of port 0 generated the interrupt External interrupt 5 is generated during the following states P0PUD 0 initial value inputs with pull down resistors setting With all P0 0 to P0 3 inputs at a L level external interrupt 5 is generated when any port 0 input changes to a H level WithanyofP0 0toP0 3inputsata H level externalinter...

Page 135: ...P0 0 P0 1 P0 2 P0 3 XI5INT QXI5 Figure 10 2 Interrupt Generation Timing of External Interrupt 5 Figure 10 3 Equivalent Circuit of External Interrupt 5 Control Level change detection circuit IE1 3 EXI5 To interrupt priority encoder circuit 128 Hz 4 kHz P0CON1 P0F Sampling signal IRQ1 IE1 IRQ1 3 QXI5 XI5INT P00IE P01IE P02IE P03IE P0IE P0 0 P0 1 P0 2 P0 3 P0PUD ...

Page 136: ... 10 4 Input Output Port Ports 4 7 Configuration VDDI P4 0 P4 3 4 4 4 A3 A0 VDDI P5 0 P5 3 4 4 4 A7 A4 VDDI P6 0 P6 3 4 4 4 A11 A8 VDDI P7 0 P7 3 4 4 4 A15 A12 4 4 Output port control Output port control Output port control Output port control P4D P4CON0 P4CON1 P5D P5CON0 P5CON1 P6D P6CON0 P6CON1 P7D P7CON0 P7CON1 P47MOD Data bus MOVXB instruction MOVXB instruction MOVXB instruction MOVXB instructi...

Page 137: ...61 P60 P6D 006H R W Port 6 output data bit 3 bit 2 bit 1 bit 0 P73 P72 P71 P70 P7D 007H R W Port 7 output data bit 3 bit 2 bit 1 bit 0 10 4 2 Port 4 7 Registers 1 Port data registers P4D P5D P6D P7D The port 4 data register P4D port 5 data register P5D port 6 data register P6D and port 7 data register P7D are 4 bit special function registers SFRs used to set the output values for the ports Port 4 ...

Page 138: ... registers are set to 0 When data is written to a port data register the actual pin change timing is at the rising edge of the system clock for state 2 of the write instruction Figure 10 5 shows port change timing S1 S2 Old data New data CLK Ports 4 7 Write instruction Figure 10 5 Port Change Timing ...

Page 139: ...S output mode Port 4 P41MD1 P41MD0 P40MD1 P40MD0 Port 4 1 output mode select bit 3 bit 2 0 0 CMOS output initial value 0 1 N channel open drain output 1 0 P channel open drain output 1 1 High impedance output Port 4 0 output mode select bit 1 bit 0 0 0 CMOS output initial value 0 1 N channel open drain output 1 0 P channel open drain output 1 1 High impedance output P4CON0 01AH R W bit 3 bit 2 bit...

Page 140: ...ial value 0 1 N channel open drain output 1 0 P channel open drain output 1 1 High impedance output P5CON0 01CH R W bit 3 bit 2 bit 1 bit 0 P53MD1 P53MD0 P52MD1 P52MD0 Port 5 3 output mode select bit 3 bit 2 0 0 CMOS output initial value 0 1 N channel open drain output 1 0 P channel open drain output 1 1 High impedance output Port 5 2 output mode select bit 1 bit 0 0 0 CMOS output initial value 0 ...

Page 141: ...l value 0 1 N channel open drain output 1 0 P channel open drain output 1 1 High impedance output P6CON0 01EH R W bit 3 bit 2 bit 1 bit 0 P63MD1 P63MD0 P62MD1 P62MD0 Port 6 3 output mode select bit 3 bit 2 0 0 CMOS output initial value 0 1 N channel open drain output 1 0 P channel open drain output 1 1 High impedance output Port 6 2 output mode select bit 1 bit 0 0 0 CMOS output initial value 0 1 ...

Page 142: ...ial value 0 1 N channel open drain output 1 0 P channel open drain output 1 1 High impedance output P7CON0 020H R W bit 3 bit 2 bit 1 bit 0 P73MD1 P73MD0 P72MD1 P72MD0 Port 7 3 output mode select bit 3 bit 2 0 0 CMOS output initial value 0 1 N channel open drain output 1 0 P channel open drain output 1 1 High impedance output Port 7 2 output mode select bit 1 bit 0 0 0 CMOS output initial value 0 ...

Page 143: ...utput to the ports 4 Voice synthesis when using an external memory When carrying out voice synthesis using an external memory ports 4 7 output the lower 16 bits of the address VA15 0 When carrying out voice synthesis using the ROM inside the chip these will be in the normal port state For details see Chapter 13 Voice Synthesis P7MOD P6MOD P5MOD P4MOD Port 7 pin function select 0 Output port functi...

Page 144: ... 6 Input Output Port Ports 8 9 and A Configuration Data bus Output port control P9D P9DIR P9CON0 P9CON1 Pull up pull down control 4 VDDI VDDI P9 0 P9 3 VSS VSS Output port control PAD PADIR PACON0 PACON1 P9AMOD Pull up pull down control VDDI VDDI PA 0 PA 3 VSS VSS 4 4 4 MOVXB instruction D3 D0 VD3 VD0 4 4 MOVXB instruction D7 D4 VD7 VD4 4 4 2 Output port control P8D P8DIR P8CON0 P8MOD Pull up pull...

Page 145: ...ports are initialized in input mode Port 8 P93DIR P92DIR P91DIR P90DIR P9DIR 029H R W bit 3 bit 2 bit 1 bit 0 Port 9 input output setting 0 Input initial value 1 Output PA3DIR PA2DIR PA1DIR PA0DIR PADIR 02CH R W bit 3 bit 2 bit 1 bit 0 Port A input output setting 0 Input initial value 1 Output Port 9 Port A Note The bits P83DIR and P82DIR have to be set to 1 or 0 before executing an external memor...

Page 146: ...nthesis 2 Port data registers P8D P9D PAD The port 8 data register P8D the port 9 data register P9D and port A data register PAD are 4 bit special function registers SFRs used to set the output values for the ports When port direction register P8DIR P9DIR PADIR bits are set to 1 and the output mode selected the contents of the port data registers are output to the ports When the output mode is sel...

Page 147: ...ts 8 9 A Write instruction Figure 10 7 Port Change Timing At system reset the port data registers are set to 0 When data is written to a port data register the actual pin change timing is at the rising edge of the system clock for state 2 of the write instruction Figure 10 7 shows port change timing ...

Page 148: ...gisters are set to 0 and all ports are initialized to pull down resistor input mode and CMOS output mode Port 8 P81MD1 P81MD0 P80MD1 P80MD0 P8CON0 023H R W bit 3 bit 2 bit 1 bit 0 Port 8 1 input output mode select Input mode bit 3 0 1 bit 2 0 0 1 Input with pull down resistor initial value Input with pull up resistor High impedance input Port 8 0 input output mode select Input mode bit 1 0 1 bit 0...

Page 149: ... mode bit 1 0 0 1 1 bit 0 0 1 0 1 CMOS output initial value N channel open drain output P channel open drain output High impedance output P93MD1 P93MD0 P92MD1 P92MD0 P9CON1 028H R W bit 3 bit 2 bit 1 bit 0 Port 9 3 input output mode select Input mode bit 3 0 1 bit 2 0 0 1 Input with pull down resistor initial value Input with pull up resistor High impedance input Port 9 2 input output mode select ...

Page 150: ...ut mode bit 1 0 0 1 1 bit 0 0 1 0 1 CMOS output initial value N channel open drain output P channel open drain output High impedance output PA3MD1 PA3MD0 PA2MD1 PA2MD0 PACON1 02BH R W bit 3 bit 2 bit 1 bit 0 Port A 3 input output mode select Input mode bit 3 0 1 bit 2 0 0 1 Input with pull down resistor initial value Input with pull up resistor High impedance input Port A 2 input output mode selec...

Page 151: ...at a system reset thereby making the ports have the normal port functions Port Secondary function Description P8 0 RD External memory read signal P8 1 WR External memory write signal P9 0 D0 Data bus of the external memory P9 1 D1 P9 2 D2 P9 3 D3 PA 0 PA 1 PA 2 PA 3 D4 D5 D6 D7 P81MOD P80MOD P8MOD 026H R W bit 3 bit 2 bit 1 bit 0 Port 8 1 pin function select 0 Input output port function initial va...

Page 152: ...hen carrying out voice synthesis using an external memory the RD signal is output at P8 0 and the data from the external memory is input via P9 P9 3 P9 0 and PA PA 3 PA 0 These pins will be in the normal port state when carrying out voice synthesis using the ROM inside the chip For details see Chapter 13 Voice Synthesis ...

Page 153: ...he circuit configuration for port B is shown in Figure 10 8 Output port control PBD PBDIR PBCON0 PBCON1 PBMOD Pull up pull down control 4 2 VDDI VDDI 4 PB 0 PB 3 VSS VSS PB 0 PB 3 to external 0 interrupt control circuit TM0OVF TM1OVF from timer 0 1 circuits TM0CAP TM1CAP T02CK T13CK to timer 0 3 circuits 4 4 Data bus Figure 10 8 Input Output Port Port B Configuration ...

Page 154: ...ut 2 Port B data register PBD PBD is a 4 bit special function register used to set the output values for port B When the port B data register is read during the output mode the content of the PBD is read The port B pin levels are read when the port B data register is read with the port B direction register bits set to 0 and the input mode selected PB3 PB2 PB1 PB0 PBD 00BH R W bit 3 bit 2 bit 1 bit...

Page 155: ...0 0 0 1 Input with pull down resistor initial value Input with pull up resistor High impedance input Output mode bit 3 0 0 1 1 bit 2 0 1 0 1 CMOS output initial value N channel open drain output P channel open drain output High impedance output Output mode bit 1 0 0 1 1 bit 0 0 1 0 1 CMOS output initial value N channel open drain output P channel open drain output High impedance output PB3MD1 PB3M...

Page 156: ... 1 capture input PB 2 T02CK Timer 0 timer 2 external clock input PB 3 T13CK Timer 1 timer 3 external clock input PB 0 TM0OVF Timer 0 overflow flag output PB 1 TM1OVF Timer 1 overflow flag output PB 0 PB 1 PB 2 INT0 External interrupt 0 PB 3 PBF PB1MOD PB0MOD PBMOD 032H R W bit 3 bit 2 bit 1 bit 0 External interrupt sampling frequency select 0 128 Hz sampling initial value 1 4 kHz sampling Port B 1...

Page 157: ...rt B are initialized to the interrupt disabled state PB3IE PB2IE PB1IE PB0IE PBIE 031H R W bit 3 bit 2 bit 1 bit 0 Port B 3 interrupt enable disable select 0 Interrupt disabled initial value 1 Interrupt enabled Port B 2 interrupt enable disable select 0 Interrupt disabled initial value 1 Interrupt enabled Port B 1 interrupt enable disable select 0 Interrupt disabled initial value 1 Interrupt enabl...

Page 158: ...one cycle of the sampling clock 128 Hz or 4 kHz Because the port B external interrupt is set by a level change at any of the port B inputs each bit of the port must be read to determine which bit of port B generated the interrupt The interrupt start address for external interrupt 0 is 0014H Figure 10 10 shows the external interrupt 0 generation timing Figure 10 11 shows the equivalent circuit for ...

Page 159: ...ration The circuit configuration for port E is shown in Figure 10 12 Figure 10 12 Input Output Port Port E Configuration Output port control PED PEDIR PECON0 PECON1 PEMOD Pull up pull down control 4 2 VDDI VDDI PE 0 PE 3 VSS VSS PE 3 to external 2 interrupt control circuit SOUT SCLK SIN SCLK to shift register circuit 1 2 from shift register circuit 4 Data bus ...

Page 160: ... Port E data register PED PED is a 4 bit special function register used to set the output values for port E When the port E direction register PEDIR is set to 1 and the output mode is selected the content of the PED is output to port E The port E pin levels are read when PED is read with the port E direction register bits set to 0 and the input mode selected PE3 PE2 PE1 PE0 PED 00EH R W bit 3 bit ...

Page 161: ...0 0 0 1 Input with pull down resistor initial value Input with pull up resistor High impedance input Output mode bit 3 0 0 1 1 bit 2 0 1 0 1 CMOS output initial value N channel open drain output P channel open drain output High impedance output Output mode bit 1 0 0 1 1 bit 0 0 1 0 1 CMOS output initial value N channel open drain output P channel open drain output High impedance output PE3MD1 PE3M...

Page 162: ...INT2 External interrupt 2 PEF PE2MOD PE1MOD PE0MOD PEMOD 040H R W bit 3 bit 2 bit 1 bit 0 External interrupt sampling frequency select 0 128 Hz sampling initial value 1 4 kHz sampling Port E 1 pin function select 0 Input output port function initial value 1 Shift register data output SOUT function goes into output mode irrespective of PE1DIR Port E 2 pin function select 0 Input output port functio...

Page 163: ... output and the interrupt request flag QXI2 is set The maximum delay for this sequence is one cycle of the sampling clock 128 Hz or 4 kHz The interrupt start address for external interrupt 2 is 0018H Figure 10 14 shows the external interrupt 2 generation timing Figure 10 15 shows the equivalent circuit for external interrupt 2 control QXI2 XI2INT PE 3 128 Hz or 4 kHz Figure 10 14 External Interrup...

Page 164: ... F Configuration The circuit configuration for port F is shown in Figure 10 16 Figure 10 16 Input Output Port Port F Configuration Output port control PFD PFDIR PFCON0 PFCON1 PFMOD Pull up pull down control PF 0 PF 3 to external interrupt 3 control circuit 4 4 VDDI VDDI PF 0 PF 3 VSS VSS Voice synthesis with an external memory used 4 Data bus VA18 VA16 ...

Page 165: ...Port F data register PFD PFD is a 4 bit special function register used to set the output values for port F When the port F direction register PFDIR is set to 1 and the output mode is selected the content of the PFD is output to port F The port F pin levels are read when PFD is read with the port F direction register bits set to 0 and the input mode selected PF3 PF2 PF1 PF0 PFD 00FH R W bit 3 bit 2...

Page 166: ...t 0 0 0 1 Input with pull down resistor initial value Input with pull up resistor High impedance input Output mode bit 3 0 0 1 1 bit 2 0 1 0 1 CMOS output initial value N channel open drain output P channel open drain output High impedance output Output mode bit 1 0 0 1 1 bit 0 0 1 0 1 CMOS output initial value N channel open drain output P channel open drain output High impedance output PF3MD1 PF...

Page 167: ...ernal interrupt sampling frequency can be selected as either 128 Hz or 4 kHz Port F secondary functions are indicated in Table 10 5 Table 10 5 Port F Secondary Functions Port Secondary function Description PF 0 PF 1 INT3 External interrupt 3 PF 2 PF 3 PFF PFMOD 045H R W bit 3 bit 2 bit 1 bit 0 External interrupt sampling frequency select 0 128 Hz sampling initial value 1 4 kHz sampling At system r...

Page 168: ...is used for selecting the interrupt enable disable state for each bit when port F is used as an external interrupt input All bits of PFIE are reset to 0 at a system reset and all port F interrupts will be initialized to the interrupt disabled state PF3IE PF2IE PF1IE PF0IE PFIE 044H R W bit 3 bit 2 bit 1 bit 0 Port F 3 interrupt disable enable select 0 Interrupt disabled initial value 1 Interrupt e...

Page 169: ...ck 128 Hz or 4 kHz Because the port F external interrupt is set by a level change at any of the port F inputs each bit of the port must be read to determine which bit of port F generated the interrupt The interrupt start address for external interrupt 3 is 001AH Figure 10 18 shows the external interrupt 3 generation timing Figure 10 19 shows the equivalent circuit for external interrupt 3 control ...

Page 170: ...Chapter 11 11 External Memory Transfer Function EXTMEM ...

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Page 172: ...d using the external memory transfer instruction MOVXB The distinction of whether to access the area of the ROM inside the chip or to access the memory area external to the chip is done by setting P83 bit 3 of P8D and P82 bit 2 of P8D Note It is not possible to access the voice synthesis section while the external memory transfer instruction is being executed Further it is also not possible to exe...

Page 173: ...name P4 0 A0 P4 1 A1 P4 2 A2 P4 3 A3 P5 0 A4 P5 1 A5 P5 2 A6 P5 3 A7 P6 0 A8 P6 1 A9 P6 2 A10 P6 3 A11 P7 0 A12 P7 1 A13 P7 2 A14 P7 3 A15 P9 0 D0 P9 1 D1 P9 2 D2 P9 3 D3 PA 0 D4 PA 1 D5 PA 2 D6 PA 3 D7 P8 0 RD P8 1 WR O P4 P5 P6 P7 secondary functions Address bus signals for external memory access P9 PA secondary functions Data bus signals for external memory access I O P8 0 secondary functions R...

Page 174: ...those being used in the secondary function as the additional address lines For example Figure 11 2 if port F PF 2 PF 0 is used for chip select the external memory space will be 64 Kbytes 8 512 Kbytes Figure 11 2 Example of Memory Space Extension Using Additional Address Lines ML63326 P7 P4 PF 2 PF 1 PF 0 External memory 1 External memory 2 External memory 8 A15 A0 CS8 A15 A0 CS2 A15 A0 CS1 16 bit ...

Page 175: ...ted Therefore these ports will become the normal output ports or I O ports In addition the pins P8 0 and P8 1 are assigned to the read signal RD and the write signal WR respectively from the moment when the secondary functions are set for them 11 5 Distinction between ROM Area inside the Chip and Memory Area External to the Chip The distinction of whether to access the area of the ROM inside the c...

Page 176: ...9AMOD 2 Set both P83DIR bit 3 of P8DIR and P82DIR bit 2 of P8DIR to 1 3 Set both P83 bit 3 of P8D and P82 bit 2 of P8D to 1 4 Execute the instruction MOVXB obj RA or MOVXB obj xadr16 Figure 11 3 shows the timing of reading data from the external memory Figure 11 3 Timing of Reading from the External Memory S1 S2 S1 S2 S1 S2 System clock P7 P4 A15 A0 PA P9 D7 D0 P8 0 RD P8 1 WR H Port setting data ...

Page 177: ...ed for executing the external memory transfer instruction P47MOD P8MOD P9AMOD 2 Set both P83DIR bit 3 of P8DIR and P82DIR bit 2 of P8DIR to 1 3 Set P83 bit 3 of P8D to 0 and P82 bit 2 of P8D to 1 4 Set PF0DIR bit 0 of PFDIR to 1 5 Set PF0 bit 0 of PFD to an address that can be read by positive logic 6 Execute the instruction MOVXB obj RA or MOVXB obj xadr16 The timing of reading is the same as tha...

Page 178: ...R to 1 3 Set both P83 bit 3 of P8D and P82 bit 2 of P8D to 1 4 Set PD3DIR bit 3 of PDDIR to 1 5 Set PD3 bit 3 of PDD to 1 6 Execute the instruction MOVXB RA obj or MOVXB xadr16 obj 7 When writing is finished set PD3 bit 3 of PDD to 0 The timing of writing data to the external memory is shown in Figure 11 4 Figure 11 4 Timing of Writing Data to the External Memory S1 S2 S1 S2 S1 S2 System clock P7 ...

Page 179: ...11 8 ML63326 User s Manual Chapter 11 External Memory Transfer Function EXTMEM ...

Page 180: ...Chapter 12 12 Melody Driver MELODY63K ...

Page 181: ......

Page 182: ...t buzzer output modes at a frequency of 4 kHz The buzzer driver signal is output via the MD and MDB pins or DACOUT and AOUT pins Melody output is a higher priority operation than buzzer output 12 2 Melody Driver Configuration The melody driver configuration is shown in Figure 12 1 Data bus Melody end interrupt request MSA instruction Melody data request Melody data 14 TEMPO MDCON Melody circuit Bu...

Page 183: ... bit 0 Melody tempo select bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 480 initial value 480 320 240 192 160 137 120 107 96 87 80 74 69 64 60 MSF EMBD MBM1 MBM0 MDCON 097H R W bit 3 bit 2 bit 1 bit 0 Melody status flag 0 Melody stopped initial value 1 Melody output Buzzer output ON OFF contr...

Page 184: ...able master interrupt MSA MDSTOP_DATA 1 Write melody end data to the melody circuit MOV A 0 2 Set the MSF flag to 0 MOV MDCON A MOV A 1101b 3 Clear melody interrupt request QMD AND IRQ0 A EI 4 Enable master interrupt MIE ROM table data part Providetwoitemsofmelodydatasothatamelodywillalwaysbeterminatedevenifamelody request is issued twice MDSTOP_DATA DW 8000H Silence data 1 DW 8000H Silence data 2...

Page 185: ... melody output forcibly describe the program in accordance with the description provided in the Note on page 12 3 If forcibly stopped the melody output cannot be restarted from the address at which it was stopped bit 1 0 MBM1 MBM0 These bits select the buzzer output mode Output of two types of intermittent tones a single tone or a continuous tone can be selected At system reset MBM1 and MBM0 are c...

Page 186: ...PO The tempos number of counts per minute set by TEMPO are shown in Table 12 1 Table 12 1 Melody Tempo 0H 1H 2H 3H 5H 6H 7H 8H 9H AH BH CH DH EH FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 480 480 320 240 160 137 120 107 96 87 80 74 69 64 60 TP3 TP2 TP1 TP0 TEMPO Tempo 4H 0 1 0 0 192 TP3 0 ...

Page 187: ...14 bitformatdataintheprogramROMdefiningtone tonelengthandendtone The melody data format is indicated in Figure 12 3 N0 N1 N2 N3 END L5 L4 L3 L2 L1 L0 N6 N5 N4 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 End bit Tone length code Tone code Bits 14 and 7 may be either 0 or 1 Tone Frequency Hz Tone code N6 N5 N4 N3 N2 N1 N0 N6 N0 Gis1 A1 Ais1 B...

Page 188: ... 0 0 0 0 25H 23H 21H 1FH 1DH 1AH 18H 17H 14H G2 1560 0 1 0 1 0 0 0 28H Dis2 E2 F2 Fis2 1490 1394 1338 1260 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 0 0 1 0 32H 2FH 2DH 2AH 2 Tone length code The tone length code is set in melody data bits 13 through 8 Table 12 3 indicates the relation between tone length and tone length code L5 to L0 The tone length that is set during execution of the MSA i...

Page 189: ...data are expressed by the following 1 953125 TP 1 L 1 ms where TP is an integer from 1 to 15 and L is an integer from 1 to 63 TP is a value set in the tempo register TEMPO and has the following bit correspondence TP 23 TP3 22 TP2 21 TP1 20 TP0 L is set by the tone length code and has a bit correspondence with the tone length code as L 25 L5 24 L4 23 L3 22 L2 21 L1 20 L0 3 END bit The END bit is se...

Page 190: ...1 1 1 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 0 1 0 0F35H 0F28H 0 0 0 1 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 0735H 0F28H 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0723H 3F1FH BF28H Note code Note G2 D2 G2 D2 G2 0700H 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0700H 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 A2 B2 G2 Fig...

Page 191: ...tput In the intermittent tone 2 mode a waveform synchronized to the logical AND of 8 Hz signal output and a L level of 1 Hz signal of the time base counter is output In the single tone mode output starts in synchronization with the rising edge of EMBD At the second falling edge of the 32 Hz output of the time base counter EMBD is cleared to 0 and output is stopped In the continuous tone mode outpu...

Page 192: ... Driver Output Waveforms in Each Output Mode EMBD 8 Hz Output MD ON OFF a MBM1 0 MBM0 0 intermittent tone 1 EMBD 8 Hz Output MD ON OFF 1 Hz EMBD 32 Hz Output MD ON OFF EMBD Output MD ON OFF b MBM1 0 MBM0 1 intermittent tone 2 c MBM1 1 MBM0 0 single tone d MBM1 1 MBM0 1 continuous tone ...

Page 193: ... melody output and the buzzer output can be made respectively at pins MD and MDB or pins DACOUT and AOUT It is possible to select which pins to output each of these waveforms using PD1 bit 1 of PDD and PD0 bit 0 of PDD Table 12 5 shows the relationship between the statuses of PD1 and PD0 and the output waveforms at each of these pins Table 12 5 Relationship between the PD1 and PD0 Statuses and Pin...

Page 194: ...ice synthesis section Forced termination of melody Set MSF bit 3 of MDCON to 1 Starts with the sound next to the one that was forcibly terminated earlier Not possible Forced starting of melody The melody interrupt MDINT is generated after reading the last melody data into the melody section The voice output interrupt VOINT is generated when the transfer of one phrase address is completed and the t...

Page 195: ...12 14 ML63326 User s Manual Chapter 12 Melody Driver MELODY63K ...

Page 196: ...13 Chapter 13 Voice Synthesis ...

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Page 198: ...is section has the functions of melody output and buzzer output in addition to voice output Each of these types of output data is stored in the internal 1 Mbit 128 Kbytes mask ROM or in the externally connected memory of up to a maximum of 4 Mbits 512 Kbytes 13 2 Voice Synthesis Section Configuration Figure 13 1 shows the configuration of the voice synthesis section ...

Page 199: ...P82 ENVOICE HSCLK BUSYB P2D P3D PCD P1D 19 19 1 1 1 1 3 8 4 3 1 2 4 4 2 3 1 Selector Selector Selector Selector Selector Selector Selector Selector Level shifter Melody buzzer Timing control section Address control circuit Interface circuit Interface circuit RD signal during the MOVXB instruction Data bus Address during the MOVXB instruction Voice synthesis core section AVDD VREF PCMOD0 PCIE 1 1 1...

Page 200: ...ts inverted every time there is a rising edge in the signal enabling the transfer of phrase data of the next sound from the voice synthesis section This is a read only bit and all write operations to this bit are ignored This bit is reset to 0 at a system reset bit 2 PC2 This is the signal corresponding to the chip select CS signal of the voice synthesis section This bit is reset to 0 at a system ...

Page 201: ... next sound phrase data This bit is set to 1 at a system reset bit 0 P10 This is the bit that monitors the BUSYB signal of the voice synthesis section This bit is set to 1 at a system reset P11 P10 P1D 001H R bit 3 bit 2 bit 1 bit 0 3 Voice synthesis control register 1 PCDIR PCDIR is a 4 bit special function register SFR for controlling the voice synthesis section PCDIR is a write only register an...

Page 202: ... for details The high order 2 bits P82 and P83 of this register are used for selecting voice synthesis or the external memory transfer instruction and for selecting the internal voice ROM area or the external memory area All these bits are reset to 0 at a system reset 6 Port 8 direction register P8DIR P8DIRisa4 bitspecialfunctionregister SFR whoselow order2bitsspecifytheinput output direction of P...

Page 203: ...er section or of the voice synthesis section is output The relationship of the selection to the status of PD0 is given below Table 13 1 Relationship between the DACOUT AOUT Outputs and the Bits PD1 and PD0 bit 0 PD0 This is the bit for selecting whether to output the melody buzzer output of the microcontroller section or of the voice synthesis section at the MD MDB pins When this bit is set to 0 t...

Page 204: ...upt sampling frequency 0 Sampling at 128 Hz initial value 1 Sampling at 4 kHz PC3IE PCIE 036H R W bit 3 bit 2 bit 1 bit 0 Voice synthesis interrupt disable enable select 0 Disabled initial value 1 Enabled 8 Voice melody buzzer output control register 1 PDDIR PDDIR is a 4 bit special function register SFR for controlling voice melody buzzer output PDDIR is a write only register and all read operati...

Page 205: ...ess management area and the user data area The test data area is the area for carrying out tests of the voice synthesis functions and cannot be used by the end user The memory configuration is the same even when carrying out voice synthesis using an externally connected ROM The maximum address of the externally connected ROM is 7FFFFH 512 Kbytes Figure 13 2 Voice ROM Configuration Test data area T...

Page 206: ...e and determine the melody buzzer sound w Determine the synthesized voice reproduction method and the sampling frequency Determine the melody tempo Determine the buzzer frequency and the output mode e Determine the correspondence between the phrase address and the voice melody buzzer sounds r Convert the data to voice data using the voice analysis tool t Voice data creation is completed Note The c...

Page 207: ...llation care should be taken because the frequency of oscillations varies due to changes in the voltage VDDH 2 times the value of VDD2 which is the power supply voltage of the high speed clock generator circuit Table 13 2 shows the relationship between the voice synthesis section input frequency and the internal sampling frequencies Table 13 2 Relationship between the Voice Synthesis Section Input...

Page 208: ...when this amplifier is not used The SP pin is the negative side output pin for driving a piezoelectric speaker and the SP pin is the positive side output pin Both pins will be at the VSS level at a system reset The MD MDB pins are used for outputting the melody buzzer output of the voice synthesis section or of the microcontroller section At a system reset both these outputs will be at a L level a...

Page 209: ...ibly terminating the voice melody or buzzer output The data of all zeroes is transferred as the stop code When the transfer of the stop code is completed all the outputs are terminated and the DACOUT pin goes to the 1 2 AVDD level Table 13 3 shows the stop code and examples of phrase addresses Table 13 3 Stop Code and Sample Phrase Addresses The test code is used for testing the voice synthesis se...

Page 210: ...fundamental unit in an adaptive manner at every sample and encodes 4 bit data thereby greatly increasing the voice waveform tracking characteristics The conversion to ADPCM data is carried out by the analysis tool The size of the voice data becomes smaller if the ADPCM method is used for human voice animals sounds and natural sounds 13 7 1 2 8 Bit Straight PCM Method This is the best method among ...

Page 211: ...he setting of PCDIR Set PC2DIR PC1DIR and PC0DIR all to 1 t Set PC2 bit 2 of PCD to 1 CS of the voice synthesis section is disabled y Enable high speed oscillation For the crystal oscillation mode Set bit 2 and bit 1 of FCON 062H to 1 For the RC oscillation mode Set bit 1 of FCON 062H to 1 Note Wait for 10 ms for crystal oscillation and 5 ms for RC oscillation so that the high speed oscillation wa...

Page 212: ...t EVI bit 3 of IE0 to 1 and repeat steps o to 3 after enabling the voice synthesis interrupt 5 Carry out the following settings for terminating the voice output Set PC1 bit 1 of PCD to 0 the voice synthesis section is put in the reset state Stop the high speed oscillation so as to reduce the supply current Reset ENOSC bit 1 of FCON to 0 Figure 13 3 shows the timing during voice synthesis output ...

Page 213: ...USYB L and goes to the H level after the sound output has been completed Voice synthesis interrupt request signal PC3 P11 BUSYB P10 DACOUT High speed clock OSC1 P3D P2D PC0 Start PC1 ENVOICE PC2 CS PCDIR r qwe 7H t 0 3 0 3 i 1 1 o o y Phrase address data transfer WAIT duration 0 V 1 2 AVDD 1 2 AVDD 1st sound output 2nd sound output Phrase address data transfer Phrase address setting of 2nd sound P...

Page 214: ...ROM capacity sampling frequency bit length Table 13 4 shows the maximum voice output duration for each sampling frequency and voice ROM capacity Table 13 4 Maximum Voice Output Duration Sampling frequency kHz Voice ROM capacity bits 512K 1M 1 5M 4 0 32 8 65 5 98 3 5 3 24 7 49 5 74 2 6 4 20 5 41 0 61 4 8 0 16 4 32 8 49 2 10 7 12 2 24 5 36 7 12 8 10 2 20 5 30 7 16 0 8 2 16 4 24 6 4 bit ADPCM method ...

Page 215: ...he END bit set to 1 is read in The generation of the melody is done using the voice analysis tool 13 9 1 Tempo Data The tempo data is set in the phrase management area at the time the ROM is manufactured It is not possible to externally change the tempo Tempo data defines the reference tone length Table 13 5 lists the set tempos the number of counts per minute Table 13 5 Melody Tempos 0H 1H 2H 3H ...

Page 216: ...P2 TP1 TP0 TEMPO Tempo 0 0 TP4 10H 0 0 0 0 73 5 1 11H 0 0 1 0 69 4 1 12H 0 0 0 1 65 8 1 13H 0 0 1 1 62 5 1 14H 0 1 0 0 59 5 1 15H 0 1 1 0 56 8 1 16H 0 1 0 1 54 3 1 17H 0 1 1 1 52 1 1 18H 1 0 0 0 50 1 19H 1 0 1 0 48 1 1 1AH 1 0 0 1 46 3 1 1BH 1 0 1 1 44 6 1 1CH 1 1 0 0 43 1 1 1DH 1 1 1 0 41 7 1 1EH 1 1 0 1 40 3 1 1FH 1 1 1 1 39 1 1 ...

Page 217: ...the melody data The frequencies that can be output by the melody circuit are defined as 65 N 2 The relation between N and tone code bits is N 27N7 26N6 25N5 24N4 23N3 22N2 21N1 20N0 If N7 through N2 are all set to 0 there is no melody output for the time specified by the tone length code Values for N1 and N0 are irrelevant Table 13 6 indicates the relations between tones and tone codes Figure 13 4...

Page 218: ...0 0 1 1 1 0 0 CCH 1 E1 0 0 1 0 0 0 0 C0H 1 F1 1 1 1 0 1 0 1 B5H 0 Fis1 1 0 1 1 0 1 1 ABH 0 G1 1 0 1 0 0 0 1 A1H 0 Gis1 0 1 1 1 0 0 0 98H 0 A1 0 0 1 1 1 1 1 8FH 0 Ais1 0 0 1 0 1 1 1 87H 0 B1 0 0 1 0 0 0 0 80H 0 C2 1 1 0 1 0 0 0 78H 1 Cis2 1 1 0 0 0 0 1 71H 1 D2 1 0 0 1 0 1 1 6BH 1 Dis2 1 0 0 0 1 0 1 65H 1 E2 0 1 0 1 1 1 1 5FH 1 F2 0 1 0 1 0 1 0 5AH 1 Fis2 0 1 0 0 1 0 0 54H 1 G2 0 1 0 0 0 0 0 50H Gi...

Page 219: ...0 0 1 1 03H 0 0 0 0 1 0 02H 0 0 0 0 0 1 01H 2 Tone length code The tone length code is set in the first byte of the melody data Table 13 7 indicates the relation between tone length and tone length code L5 to L0 When all bits are set to 0 the tone length will be the same as the minimum tone length the tone length with only L0 set to 1 The tone will be a rest when N6 to N0 are all set to 0 in the s...

Page 220: ...ollowing bit correspondence TP 24 TP4 23 TP3 22 TP2 21 TP1 20 TP0 L is set by the tone length code and has a bit correspondence with the tone length code as L 25L5 24L4 23L3 22L2 21L1 20L0 3 END bit The END bit is set in bit 15 of the melody data When the output of the last melody data with the END bit set to 1 is started the melody circuit generates a melody end signal and stops the melody after ...

Page 221: ...t byte can be either 0 or 1 but is shown here as 0 4 4 120 7 6 5 4 3 2 END L5 L4 L3 L2 1 0 7 L1 L0 N7 6 5 4 3 2 1 N6 N5 N4 N3 N2 N1 0 N0 Hex value 0 0 0 2F50H 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 1 0 1 1 0 1 1 1 0 0 1 1 1 0F6BH 1750H 0 0 0 0 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 1 1 0 1 0 1 076BH 1750H 0 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 1 1 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1...

Page 222: ...DACOUT AOUT and MD MDB Set PD1DIR and PD0DIR bit 1 and bit 0 of PDDIR to 1 When outputting at MD MDB Set PD1 and PD0 bit 1 and bit 0 of PDD to 1 When outputting at DACOUT AOUT Set PD1 to 1 and PD0 to 0 w Select voice synthesis external memory transfer instruction Set P82DIR bit 2 of P8DIR to 1 Set P82 bit 2 of P8D to 0 e Select the internal voice ROM or the external memory Set P83DIR bit 3 of P8DI...

Page 223: ...melody output has been completed Voice synthesis interrupt request signal PC3 P11 BUSYB When outputting at DACOUT AOUT High speed clock OSC1 P3D P2D PC0 PC1 ENVOICE PC2 PCDIR r qwe 7H t 0 3 0 3 i 1 1 o o y Phrase address data transfer 0 V 1 2 AVDD 1st melody output 2nd melody output 2 2 When outputting at MD MDB 1st melody output 2nd melody output 0 V Phrase address data transfer Phrase address se...

Page 224: ...ency can be selected from the 50 duty ratio frequencies of 0 5 kHz 1 0 kHz and 2 0 kHz and the buzzer output mode can be selected from intermittent tone 1 intermittent tone 2 single tone and continuous tone The output waveforms in the different output modes is shown in Figure 13 7 The dark filled parts in the waveform indicate the output frequency signal 0 5 1 0 or 2 0 kHz Figure 13 7 Buzzer Drive...

Page 225: ... PC2 bit 2 of PCD to 1 CS of the voice synthesis section is disabled y Enable high speed oscillation For the crystal oscillation mode Set bit 2 and bit 1 of FCON 062H to 1 For the RC oscillation mode Set bit 1 of FCON 062H to 1 Note Wait for 10 ms for crystal oscillation and 5 ms for RC oscillation so that the high speed oscillation waveform becomes stable u The contents of the program differ depe...

Page 226: ...es by connecting a 512 Kbyte ROM externally An example of connections to be made for this expansion is shown in Figure 13 8 Figure 13 8 Example of Connections Made When an External ROM is Used VDD VDDI VSS PF 2 PF 1 PF P7 P6 P5 P4 PA P9 PF 0 P7 3 P7 2 P7 1 P7 0 P6 3 P6 2 P6 1 P6 0 P5 3 P5 2 P5 1 P5 0 P4 3 P4 2 P4 1 P4 0 PA 3 PA 2 PA 1 PA 0 P9 3 P9 2 P9 1 P9 0 P8 0 A18 A17 A16 A15 A14 A13 A12 A11 A...

Page 227: ...ce R1 is 50 kW and R2 is 100 kW the amplitude of the AOUT output is increased twofold and is output to the SP and SP pins When selecting R1 and R2 make sure that the sum of R1 and R2 is 100 kW or more By connecting the SPEN pin with the ENVOICE pin as shown below the amplifiers will also become enabled only when the voice synthesis section is enabled Figure 13 9 Example of Connections Made When Us...

Page 228: ...14 Chapter 14 Shift Register SFT ...

Page 229: ......

Page 230: ...data transfer is completed a shift register interrupt request is generated 14 2 Shift Register Configuration The shift register configuration is shown in Figure 14 1 PE 0 SIN PE1 SOUT and PE 2 SCLK are the shift data input pin the shift data output pin and the shift clock input output pin respectively Set the secondary function by using port mode register D Q CK R Transfer complete Control circuit...

Page 231: ...egister L H SFTRL SFTRH SFTRLandSFTRHare4 bitspecialfunctionregisters SFRs usedtowriteshiftregistersend data and to read receive data SD3 SD2 SD1 SD0 SFTRL 0A0H R W bit 3 bit 2 bit 1 bit 0 SD7 SD6 SD5 SD4 SFTRH 0A1H R W bit 3 bit 2 bit 1 bit 0 SFTRL and SFTRH are set to 0 at system reset ...

Page 232: ...nitial value 0 1 1 2 CLK 1 0 Timer 1 overflow 1 1 External clock bit 2 SDIR This bit selects the transfer order for 8 bit send receive data When the SDIR bit is 0 it means MSB first and when 1 LSB first bit 1 0 SELCK1 SELCK0 These bits select the shift clock If set to CLK 1 2 CLK or timer 1 overflow the system operates in master mode If set to external clock the system operates in slave mode ENTR ...

Page 233: ... shift clock falling edge and shift out data is output from the first bit through the PE 1 SOUT pin In synchroni zation with the shift clock rising edge shift in data is input from the first bit through the PE 0 SIN pin For external devices shift in data changes on the falling edge of the shift clock and shift out data changes on the rising edge of the shift clock When 8 bit data transfer is compl...

Page 234: ... System clock SFTINT Figure 14 2 Shift Register Operation Timing Note Setting the ENTR bit to 1 in the slave mode should be done when the PE 2 SCLK pin is high If SFTRL SFTRH are written during transfer the transfer data send and receive is destroyed In this case terminate the transfer and start over again Even when receiving only transfer begins with setting the ENTR bit to 1 ...

Page 235: ...1 SELCK0 SFTCON0 bits 1 0 master slave mode select 3 SelectMSBfirstorLSBfirstwithSDIR SFTCON0bit2 0 forMSBfirst 1 forLSBfirst 4 Set ESFT IE3 bit 2 to 1 and enable the shift register interrupt 5 Set the MIE master interrupt enable flag to 1 and enable all interrupts 6 Write send data to SFTRL and SFTRH 7 Set ENTR bit 0 of SFTCON1 to 1 and start the transfer With the above settings the shift registe...

Page 236: ...15 Chapter 15 LCD Driver LCD ...

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Page 238: ...eg 16 com dots The LCD driver can be software selected to all OFF all ON or power down mode 1 4 or 1 5 bias selectable duty from 1 1 to 1 16 and adjustable 16 tone contrast 15 2 LCD Driver Configuration The LCD driver configuration is shown in Figure 15 1 Data bus BIAS generator LCD controller Display register 64 4 nibbles Common driver Segment driver COM1 COM16 SEG0 SEG63 Figure 15 1 LCD Driver C...

Page 239: ...current At system reset it is cleared to 0 bit 1 ALLON When ALLON is set to 1 all segment drivers are turned on The ALLON bit has priority over the LCDON bit At system reset it is cleared to 0 bit 0 LCDON When the LCDON bit is set to 1 the display data in the display register is output to the segment drivers At system reset it is cleared to 0 and all segment drivers are turned off BISEL PDWN ALLON...

Page 240: ...1 1 duty 0 0 1 0 1 2 duty 0 0 1 1 1 3 duty 0 1 0 0 1 4 duty 0 1 0 1 1 5 duty 0 1 1 0 1 6 duty 0 1 1 1 1 7 duty 1 0 0 0 1 8 duty 1 0 0 1 1 9 duty 1 0 1 0 1 10 duty 1 0 1 1 1 11 duty 1 1 0 0 1 12 duty 1 1 0 1 1 13 duty 1 1 1 0 1 14 duty 1 1 1 1 1 15 duty bit 3 bit 2 bit 1 bit 0 2 Display control register DSPCON1 DSPCON1 is a 4 bit special function register SFR used to select the LCD driver duty At s...

Page 241: ...COM1 DSPR4 104H R W bit 3 bit 2 bit 1 bit 0 COM8 COM7 COM6 COM5 DSPR5 105H R W bit 3 bit 2 bit 1 bit 0 COM12 COM11 COM10 COM9 DSPR6 106H R W bit 3 bit 2 bit 1 bit 0 COM16 COM15 COM14 COM13 DSPR7 107H R W bit 3 bit 2 bit 1 bit 0 Segment 1 output data COM4 COM3 COM2 COM1 DSPR252 1FCH R W bit 3 bit 2 bit 1 bit 0 COM8 COM7 COM6 COM5 DSPR253 1FDH R W bit 3 bit 2 bit 1 bit 0 COM12 COM11 COM10 COM9 DSPR2...

Page 242: ...tops and COM1 16 and SEG0 63 pins are all output at the VSS level to reduce supply current BISEL bit3 of DSPCON0 selects 1 4 or 1 5 bias DSPCNT controls the LCD contrast of 16 tones VDDH 2 4 V or more When the LCD driver is not used select the power down mode and set all the bits of the display control register DSPCNT to 0 to save the supply current Table 15 1 Frame Frequency for Each Duty DSPCON1...

Page 243: ...ation circuit in order to reduce supply current Figure 15 2 shows the bias generator configuration for 1 5 bias and Figure 15 3 shows the configuration for 1 4 bias For details of the voltage doubler circuit and the constant voltage circuit see Chapter 17 Power Supply Circuit Tables 15 2 and 15 3 list the display contrast adjusting voltages Voltage doubler circuit Display contrast adjustment CN3 0...

Page 244: ... 1 4 Bias Display contrast adjustment CN3 0 1 4 bias select BISEL 1 To LCD driver Constant voltage circuit BIAS generator CB1 CB2 VDD5 VDD4 VDD3 VDD2 VDD1 VSS C1 VSS C2 C12 Ca Cb Cd Ce Cb12 Power down mode select PDWN 1 VDDL Cl Voltage doubler circuit VDDH Ch VDD To high speed clock generator circuit ...

Page 245: ...90 2 00 2 10 6H 0 1 1 0 1 94 2 04 2 14 7H 0 1 1 1 1 98 2 08 2 18 8H 1 0 0 0 2 02 2 12 2 22 9H 1 0 0 1 2 06 2 16 2 26 0AH 1 0 1 0 2 10 2 20 2 30 0BH 1 0 1 1 2 14 2 24 2 34 0CH 1 1 0 0 2 18 2 28 2 38 0DH 1 1 0 1 2 22 2 32 2 42 0EH 1 1 1 0 2 26 2 36 2 46 0FH 1 1 1 1 2 30 2 40 2 50 Light Dark Ta 25 C VSS 0 V BISEL Mode Voltage V Power supply Min Typ Max 0 1 5 bias VDD1 Typ 0 1 1 2 VDD2 Typ 0 1 VDD3 Ty...

Page 246: ...1 16 duty and 1 5 bias and Figures 15 5 a and 15 5 b show the output waveforms for 1 8 duty and 1 4 bias Figure 15 4 a 1 16 Duty 1 5 Bias Common Output Waveform VSS VDD1 VDD2 VDD3 VDD4 VDD5 1 2 3 4 5 16 1 2 3 4 5 16 VSS VDD1 VDD2 VDD3 VDD4 VDD5 VSS VDD1 VDD2 VDD3 VDD4 VDD5 VSS VDD1 VDD2 VDD3 VDD4 VDD5 Frame frequency 64 Hz COM1 COM2 COM3 COM16 ...

Page 247: ...10 11 12 13 14 15 16 Frame frequency 64 Hz SEG0 SEG1 SEG2 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG0 SEG1 SEG2 SEG3 SEG4 VDD5 VDD4 VDD3 VDD2 VDD1 VSS VDD5 VDD4 VDD3 VDD2 VDD1 VSS VDD5 VDD4 VDD3 VDD2 VDD1 VSS Figure 15 4 b 1 16 Duty 1 5 Bias Segment Output Waveform ...

Page 248: ... VDD4 VDD2 3 VDD1 VSS VDD5 VDD4 VDD2 3 VDD1 VSS VDD5 VDD4 VDD2 3 VDD1 VSS COM1 COM2 COM3 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Frame frequency 128 Hz VDD5 VDD4 VDD2 3 VDD1 VSS COM8 VDD5 VDD4 VDD2 3 VDD1 VSS COM9 16 Figure 15 5 a 1 8 Duty 1 4 Bias Common Output Waveform ...

Page 249: ...DD4 VDD2 3 VDD1 VSS VDD5 VDD4 VDD2 3 VDD1 VSS VDD5 VDD4 VDD2 3 VDD1 VSS SEG0 SEG1 SEG2 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Frame frequency 128 Hz COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1 SEG2 SEG3 SEG4 Figure 15 5 b 1 8 Duty 1 4 Bias Segment Output Waveform ...

Page 250: ...16 Chapter 16 Battery Low Detect Circuit BLD ...

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Page 252: ...CON bits Judgment voltage values Ta 25 C 2 00 0 10 V 2 20 0 10 V 2 40 0 10 V Note When verifying BLD operation the operation must be verified with an evaluation sample device The development support tool EASE63180 does not support BLD 16 2 Battery Low Detect Circuit Configuration The battery low detect circuit consists of a judgment circuit and a judgment voltage select circuit Figure 16 1 shows t...

Page 253: ...value BLDCON 094H R W bit 3 bit 2 bit 1 bit 0 Judgment voltage select bit 1 bit 0 0 0 Undefined initial value 0 1 2 00 0 10 V 1 0 2 20 0 10 V 1 1 2 40 0 10 V Battery low detect circuit ON OFF control 0 Battery low detect circuit OFF initial value 1 Battery low detect circuit ON bit 3 BLDF This flag indicates the judgement result of the battery low detect circuit This bit is set to 1 when VDD is lo...

Page 254: ... is 0 the power supply voltage is higher than the judgment voltage BLDF is valid when ENBL is 1 The judgment circuit of the battery low detect circuit requires time to become stable Therefore after setting ENBL to 1 wait at least 1 ms before reading BLDF No load should be applied to the power supply voltage during the detection Figure 16 2 shows an example operation timing Judgment voltage Vcmp BL...

Page 255: ...16 4 ML63326 User s Manual Chapter 16 Battery Low Detect Circuit BLD ...

Page 256: ...Chapter 17 17 Power Supply Circuit POWER ...

Page 257: ......

Page 258: ...supply VDD2 and a voltage doubler circuit for the power supply for high speed oscillation VDDH 17 2 Power Supply Circuit Configuration Figure 17 1 shows the power supply circuit configuration Figure 17 1 Power Supply Circuit Configuration OSC1 OSC0 High speed clock generator circuit Constant voltage circuit Bias generator VDD VDDH CB1 CB2 VDD5 VDD4 VDD3 VDD2 VDD1 C1 C2 VSS C12 Ca Cb Cc Cd Ce Cb12 ...

Page 259: ... by the display contrast register DSPCNT immediately after the reset state is released The VDDH output of the power supply for high speed oscillation becomes about 1 2 V after the time base counter is reset and while the high speed oscillations have been stopped ENOSC 0 because it is connected via VDD2 and a diode When the high speed oscillations are started ENOSC 1 the voltage doubler circuit sta...

Page 260: ...Appendixes ...

Page 261: ......

Page 262: ... P23 0H P22 P21 P20 Port 3 data register R W P3D 003H P33 0H P32 P31 P30 Port 4 data register R W P4D 004H P43 0H P42 P41 P40 Port 5 data register R W P5D 005H P53 0H P52 P51 P50 Port 6 data register R W P6D 006H P63 0H P62 P61 P60 Port 7 data register R W P7D 007H P73 0H P72 P71 P70 Port 8 data register R W P8D 008H P83 0H P82 P81 P80 Port C data register R W PCD 00CH PC3 1 0H PC2 PC1 PC0 Port D ...

Page 263: ...PB2DIR PB2IE PE3MD0 PE2DIR bit 1 P90MD1 P92MD1 P91DIR PA0MD1 PA2MD1 PA1DIR PB0MD1 PB2MD1 PB1DIR PB1IE PB1MOD PE2MD1 PE1DIR bit 0 P90MD0 P92MD0 P90DIR PA0MD0 PA2MD0 PA0DIR PB0MD0 PB2MD0 PB0DIR PB0IE PB0MOD PE2MD0 PE0DIR Port 8 direction register R W P8DIR 025H P83DIR 0H P82DIR P81DIR P80DIR Port 8 mode register R W P8MOD 026H 0CH P81MOD P80MOD R W P9AMOD 0CH PAMOD P9MOD Port D direction register W ...

Page 264: ...ounter register H R W 0H Symbol IE0 IE1 IE2 IE3 IE4 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 TBCR0 TBCR1 FCON T100CR T10CR T100CON TM0DL TM0DH TM1DL TM1DH TM0CL TM0CH TM1CL TM1CH Address 050H 051H 052H 053H 054H 055H 056H 057H 058H 059H 05AH to 05FH 060H 061H 062H 063H 064H 065H 066H 067H 068H 069H 06AH 06BH 06CH 06DH 06EH 06FH bit 3 EVI EXI5 ETM3 E10Hz E2Hz Q2Hz QVI QXI5 QTM3 Q10Hz 16Hz 1Hz 100C3 10C3 T0D3 T0D7 ...

Page 265: ...ontrol register W Symbol TM2DL TM2DH TM3DL TM3DH TM2CL TM2CH TM3CL TM3CH TM2CON0 TM2CON1 TM2STAT TM3STAT TM3CON0 TM3CON1 DSPCON0 DSPCON1 DSPCNT BLDCON TEMPO MDCON WDTCON Address 076H 077H 078H 079H 07AH 07BH 07CH 07DH 07EH 07FH 080H 081H 082H 083H 084H to 08FH 090H 091H 092H 093H 094H 095H 096H 097H 098H to 09EH 09FH bit 3 T2D3 T2D7 T3D3 T3D7 T2C3 T2C7 T3C3 T3C7 BISEL DT3 CN3 BLDF TMP3 MSF d3 bit ...

Page 266: ...0FFH bit 3 sp3 y3 x3 l3 h3 c3 e3 R 0EH bit 2 sp2 y2 x2 l2 h2 c2 e2 bit 1 sp1 y1 x1 l1 h1 c1 e1 bit 0 sp0 y0 x0 l0 h0 c0 e0 MIE Shift register L R W 0H Shift register H R W 0H Shift register control register 0 R W 8H Shift register control register 1 R W 0EH Reserved RA register 0 R W 0H RA register 1 R W 0H RA register 2 R W 0H RA register 3 R W 0H Register stack pointer SFTRL SFTRH SFTCON0 SFTCON...

Page 267: ...R15 10FH COM16 R W Undefined COM15 COM14 COM13 Display register 16 DSPR16 110H COM4 R W Undefined COM3 COM2 COM1 Display register 17 DSPR17 111H SEG4 COM8 R W Undefined COM7 COM6 COM5 Display register 18 DSPR18 112H COM12 R W Undefined COM11 COM10 COM9 Display register 19 DSPR19 113H COM16 R W Undefined COM15 COM14 COM13 Display register 20 DSPR20 114H COM4 R W Undefined COM3 COM2 COM1 Display reg...

Page 268: ...W Undefined COM7 COM6 COM5 Display register 50 DSPR50 COM12 R W Undefined COM11 COM10 COM9 Display register 51 DSPR51 COM16 R W Undefined COM15 COM14 COM13 Display register 52 DSPR52 COM4 R W Undefined COM3 COM2 COM1 Display register 53 DSPR53 SEG13 COM8 R W Undefined COM7 COM6 COM5 Display register 54 DSPR54 COM12 R W Undefined COM11 COM10 COM9 Display register 55 DSPR55 COM16 R W Undefined COM15...

Page 269: ...SPR87 157H 158H 159H 15AH 15BH 168H 169H 16AH 16BH 15CH 15DH 15EH 15FH 160H 161H 162H 163H 164H 165H 166H 167H COM16 R W Undefined COM15 COM14 COM13 Display register 88 DSPR88 COM4 R W Undefined COM3 COM2 COM1 Display register 89 DSPR89 SEG22 COM8 R W Undefined COM7 COM6 COM5 Display register 90 DSPR90 COM12 R W Undefined COM11 COM10 COM9 Display register 91 DSPR91 COM16 R W Undefined COM15 COM14 ...

Page 270: ...7 COM8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM14 COM13 COM4 R W Undefined COM3 COM2 COM1 SEG28 COM8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM14 COM13 COM4 R W Undefined COM3 COM2 COM1 SEG29 COM8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM...

Page 271: ...8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM14 COM13 COM4 R W Undefined COM3 COM2 COM1 SEG37 COM8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM14 COM13 COM4 R W Undefined COM3 COM2 COM1 SEG38 COM8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM14 CO...

Page 272: ...8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM14 COM13 COM4 R W Undefined COM3 COM2 COM1 SEG46 COM8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM14 COM13 COM4 R W Undefined COM3 COM2 COM1 SEG47 COM8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM14 CO...

Page 273: ...G55 COM8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM14 COM13 COM4 R W Undefined COM3 COM2 COM1 SEG56 COM8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 COM14 COM13 COM4 R W Undefined COM3 COM2 COM1 SEG57 COM8 R W Undefined COM7 COM6 COM5 COM12 R W Undefined COM11 COM10 COM9 COM16 R W Undefined COM15 C...

Page 274: ...t Type Package The SOP QFP TSOP TQFP LQFP SOJ QFJ PLCC SHP and BGA are surface mount type packages which are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person on the product name package name pin number package code and desired mounting conditions reflow method temperature and times ...

Page 275: ...PF 0 PF 3 2 Input Port P0 0 P0 3 VSS VDDI VDDI VSS VDDI I O Gate control circuit Pull up pull down control Output data Output control Input data Schmitt trigger input VSS VDDI VDDI I Pull up pull down control Input data Schmitt trigger input 3 Output Port P4 0 P4 3 P5 0 P5 3 P6 0 P6 3 P7 0 P7 3 VDDI VSS O Gate control circuit Output data Output control ...

Page 276: ... input VDD VSS Inside the IC XT0 Time base clock TBCCLK XT1 VDD2 Inside the IC CMOS input OSC0 VDDH OSC1 CMOS input High speed clock HSCLK Oscillation start Inside the IC 3 Low Speed Clock Generator 4 High Speed Clock Generator 5 RESET TST1 TST2 VTEST and SPEN Inputs ...

Page 277: ...r reference RESET Push button switch Connect these pins COM1 16 SEG0 63 ML63326 External memory 512K 8 bits GND 5 0 V VDD A18 LCD R2 200 kW R1 100 kW 0 1 mF Piezoelectric speaker CG 32 768 kHz crystal 5 to 25 pF Ch 2 0 to 5 5 V 1 0 mF CB1 CB2 Cb12 1 0 mF VDDL Cl A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PF 2 PF 1 PF 0 P7 3 P7 2 P7 1 P7 0 P6 3 P6 2 P6 1 P6 0 P5 3 P5 2 P5 1 P5 0 ...

Page 278: ... switch Connect these pins COM1 16 SEG0 63 ML63326 External memory 512K 8 bits GND 5 0 V VDD A18 LCD R2 200 kW R1 100 kW 0 1 mF Piezoelectric speaker ROSL 1 5 MW approx 32 kHz Ch 2 0 to 5 5 V 1 0 mF CB1 CB2 Cb12 1 0 mF VDDL Cl A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PF 2 PF 1 PF 0 P7 3 P7 2 P7 1 P7 0 P6 3 P6 2 P6 1 P6 0 P5 3 P5 2 P5 1 P5 0 P4 3 P4 2 P4 1 P4 0 PF 3 VDDI D7 D6 ...

Page 279: ...CG are only for reference RESET Push button switch Connect these pins COM1 16 SEG0 63 ML63326 External memory 512K 8 bits GND 5 0 V VDD A18 R2 200 kW R1 100 kW 0 1 mF Piezoelectric speaker CG 32 768 kHz crystal 5 to 25 pF Ch 2 0 to 5 5 V 1 0 mF CB1 CB2 Cb12 1 0 mF VDDL Cl A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PF 2 PF 1 PF 0 P7 3 P7 2 P7 1 P7 0 P6 3 P6 2 P6 1 P6 0 P5 3 P5 2 ...

Page 280: ...Cb12 C12 Ch CV CL0 CL1 and CG are only for reference RESET Push button switch COM1 16 SEG0 63 ML63326 External memory 512K 8 bits GND 5 0 V VDD A18 LCD CG 32 768 kHz crystal 5 to 25 pF Ch 2 0 to 5 5 V 1 0 mF CB1 CB2 Cb12 1 0 mF VDDL Cl A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PF 2 PF 1 PF 0 P7 3 P7 2 P7 1 P7 0 P6 3 P6 2 P6 1 P6 0 P5 3 P5 2 P5 1 P5 0 P4 3 P4 2 P4 1 P4 0 PF 3 VD...

Page 281: ...or Ca Cb Cc Cd Ce Cl Cb12 C12 Ch CV CL0 CL1 CVO and CG are only for reference RESET Push button switch Connect these pins COM1 16 SEG0 63 ML63326 LCD R2 200 kW R1 100 kW 0 1 mF Piezoelectric speaker CG 32 768 kHz crystal 5 to 25 pF Ch 2 0 to 5 5 V 1 0 mF CB1 CB2 Cb12 1 0 mF VDDL Cl PF 2 PF 1 PF 0 P7 3 P7 2 P7 1 P7 0 P6 3 P6 2 P6 1 P6 0 P5 3 P5 2 P5 1 P5 0 P4 3 P4 2 P4 1 P4 0 PF 3 VDDI PA 3 PA 2 PA...

Page 282: ...DI input Ta 25 C VIN2 V 0 3 to VDD1 0 3 Output Voltage 1 VDD1 output Ta 25 C VOUT1 V 0 3 to VDD2 0 3 Output Voltage 2 VDD2 output Ta 25 C VOUT2 V 0 3 to VDD3 0 3 Output Voltage 3 VDD3 output Ta 25 C VOUT3 V 0 3 to VDD4 0 3 Output Voltage 4 VDD4 output Ta 25 C VOUT4 V 0 3 to VDD5 0 3 Output Voltage 5 VDD5 output Ta 25 C VOUT5 V 0 3 to VDD 0 3 Output Voltage 6 VDD output Ta 25 C VOUT6 V 0 3 to VDDI ...

Page 283: ...ndition Range Unit Operating Temperature Top 20 to 70 C VDD 2 0 to 5 5 Operating Voltage VSS 0 V High speed RC Oscillation Frequency fROSH 1 8 30 ROSH 39 kW 4 096 MHz VDDH 3 6 to 5 5 V MHz ROSH 47 kW Low speed RC Oscillation Frequency fROSL kHz 2 0 30 60 30 ROSL 700 kW 32 30 ROSL 1 5 MW 80 30 ROSL 400 kW VDDH 3 6 to 5 0 V AVDD 2 0 to 5 5 VREF 0 5 to AVDD 1 0 V Recommended Operating Conditions ...

Page 284: ...l characteristics of low speed RC oscillation When VDD2 1 8 V 1000 100 10 100 1000 10000 f ROSL kHz ROSL kW Reference data Typical characteristics of high speed RC oscillation When VDDH 3 6 V 10000 1000 100 10 100 1000 f ROSH kHz ROSH kW Reference data ...

Page 285: ...d Internal Crystal Oscillator Capacitance CD pF 16 12 8 High speed Internal RC Oscillator Capacitance COS pF 20 8 5 High speed External Crystal Oscillator Capacitance CL0 1 AT 49 4 096 MHz Daishinku Corp make used VDD 5 0 V pF 1 1 8 V 2 2 1 7 1 2 VDDL Voltage VDDL High speed clock oscillation stopped V 5 5 2 0 High speed clock oscillation VDD 2 0 to 5 5 V V VDDH 3 7 3 6 2 0 VDDH Voltage High speed...

Page 286: ...s from VDD to VPOR2 and again rises up to VDD DC Characteristics continued Parameter Symbol Condition Mea suring Circuit Unit Max Typ Min VDD VDDI AVDD 2 0 to 5 5 V VSS AVSS 0 V Ta 20 to 70 C unless otherwise specified 2 5 2 4 2 3 BLD Judgment Voltage VBLDC LD1 1 LD0 1 Ta 25 C 2 3 2 2 2 1 LD1 1 LD0 0 Ta 25 C V 2 1 2 0 1 9 LD1 0 LD0 1 Ta 25 C 3 5 BLD Judgment Voltage Temperature Deviation DVBLDC VB...

Page 287: ...pply Current 3 IDD3 CPU is in operation at low speed oscillation High speed clock oscillation stopped mA 1 12 2 10 0 1 5 Ta 20 to 50 C Ta 20 to 50 C Ta 20 to 70 C Ta 20 to 70 C 650 500 Supply Current 4 IDD4 CPU is in operation at high speed oscillation RC oscillation ROSH 47 kW mA 1000 800 Supply Current 5 IDD5 CPU is in operation at high speed oscillation Crystal oscillation 4 096 MHz mA Ta 20 to...

Page 288: ... mA 4 0 mA 6 0 9 0 11 0 14 0 AVDD 3 0 V AVDD 5 0 V IOL2 VOL2 0 7 V 11 0 mA 14 0 mA 5 5 7 0 2 0 4 0 AVDD 3 0 V AVDD 5 0 V Output Current 3 SEG0 to SEG63 COM1 to COM16 4 mA IOHM3 mA mA 4 mA IOMH3S mA mA VDD VDDH 3 0 V VDD VDDH 5 0 V 0 5 mA 1 7 3 5 IOL4R VOL4R 0 5 V RC oscillation 2 5 mA 1 5 0 25 VDD VDDH 3 0 V VDD VDDH 5 0 V 3 5 mA 1 8 0 5 IOH4C VOH4C VDDH 0 5 V crystal oscillation 100 mA 250 500 VD...

Page 289: ...C oscillation 1 0 mA 0 0 IIL2R VIL2R VSS RC oscillation 0 0 mA 1 0 4 0 mA IIH2C VIH2C VDDH crystal oscillation 10 mA 2 0 6 0 5 3 VDD VDDH 3 0 V VDD VDDH 5 0 V 0 5 mA IIL2C VIL2C VSS crystal oscillation 3 mA 2 0 6 4 0 10 VDD VDDH 3 0 V VDD VDDH 5 0 V VDD 5 0 V 5 0 mA 2 7 0 5 IIL3 VIL3 VSS 0 0 mA 1 0 Input Current 4 TST1 TST2 VTEST IIH4 VIH4 VDD VDD 3 0 V 5 5 mA 3 0 0 5 VDD 5 0 V 11 0 mA 6 5 2 0 IIL...

Page 290: ...RESET TST1 TST2 SPEN VIL1 VDDI 3 0 V 0 0 0 6 V VDDI 5 0 V 0 0 1 0 V VDD VDDH 3 0 V 2 4 3 0 V VIH2 VDD VDDH 5 0 V 4 0 5 0 V VDD VDDH 3 0 V 0 0 0 6 V VIL2 VDD VDDH 5 0 V 0 0 1 0 V Input Voltage 3 RESET TST1 TST2 VTEST SPEN VIH3 VDD 3 0 V 2 4 3 0 V VDD 5 0 V 4 0 5 0 V VIL3 VDD 3 0 V 0 0 0 6 V VDD 5 0 V 0 0 1 0 V DVT1 VDDI 3 0 V 0 2 0 5 1 0 V VDDI 5 0 V 0 25 1 0 1 5 V Hysteresis Width 1 P0 0 to P0 3 P...

Page 291: ...he specified output pins AVSS AVDD VREF Cb12 CB1 CB2 C12 C1 C2 OSC0 q OSC1 w 1 VSS A VDD VDDI VDD1 V Ca VDD2 V Cb VDD3 V Cc VDD4 V Cd VDD5 V Ce VDDH V Ch XT0 XT1 Ca Cb Cc Cd Ce Cl C12 Cb12 Ch CG CL0 CL1 Crystal unit 0 1 mF 1 mF 15 pF 30 pF 30 pF AT 49 4 096 MHz Daishinku Corp make CL0 CL1 q w q w 1 RC Oscillator ROSH Crystal Oscillator Crystal VDDL V Cl 2 e r AVSS AVDD VREF CG e r e r 2 RC Oscilla...

Page 292: ... circuit 3 VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH INPUT OUTPUT A 5 VDDL AVSS AVDD VREF Measuring circuit 4 VSS VIH VIL 5 VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH INPUT OUTPUT 5 Measured at the specified input pins Waveform Monitoring VDDL AVSS AVDD VREF ...

Page 293: ...K Input Rise Time tr ms 1 0 0 8 SCLK Input L Level Pulse Width tCWL ms 0 8 SCLK Input H Level Pulse Width tCWH ms 1 8 SCLK Input Cycle Time tCYC VDDI 5 V to VDD ms SCLK Output Cycle Time tCYC1 O CPU in operation state at 32 768 kHz ms 30 5 tCYC2 O CPU in operation at 2 MHz VDD 2 0 V to 5 5 V ms 0 5 SOUT Output Delay Time tDDR Cl 10 pF ms 0 4 0 5 SIN Input Setup Time tDS ms 0 8 SIN Input Hold Time ...

Page 294: ...ol Condition Unit Read Cycle Time Max Typ Min tRC 61 RD Output Delay Time tOE 5 Output Valid Time tOHA ms 5 External Memory Output Delay Time tDO 5 Parameter Symbol Condition Unit 1 Read Cycle Time Max Typ Min tRC RD Output Delay Time tOE 100 Output Valid Time tOHA ns 100 External Memory Output Delay Time tDO 150 ms S1 S2 S1 S2 S1 S2 System clock P7 P4 A15 A0 P8 1 WR Port setup value Address outpu...

Page 295: ...3 Write Recovery Time tWR 15 3 Data Setup Time tDS 45 8 Data Hold Time tDH 15 3 Parameter Symbol Condition Unit 1 Write Cycle Time Max Typ Min tWC 0 4 Address Setup Time tAS 0 2 Write Time tW ms 0 2 Write Recovery Time tWR 0 7 Data Setup Time tDS 0 2 Data Hold Time tDH S1 S2 S1 S2 S1 S2 System clock P7 P4 A15 A0 PA P9 D7 D0 Port setup value Address output Port setup value tWC VDDI VSS P8 1 WR VDDI...

Page 296: ...s marked with are affected by instruction execution and those that are not affected with a dash Indicates the instruction code content For a 2 word long instruction the first row shows the first word and the second row the second word Indicates the number of machine cycles needed to execute the instruction Indicates the instruction word length Indicates the instruction function Indicates the short...

Page 297: ...1 1 1 i3 i2 i1 i0 0 MOV E HL i4 E HL A i4 HL HL 1 1 1 0 0 0 0 1 1 1 0 1 0 0 i3 i2 i1 i0 0 MOV E XY i4 E XY A i4 XY XY 1 1 1 0 0 0 0 1 1 1 0 1 0 1 i3 i2 i1 i0 0 MOV A i4 A i4 1 1 0 0 0 0 0 0 1 1 1 0 0 i3 i2 i1 i0 1 MOV A direct A direct 1 1 1 0 1 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 0 MOV A HL A HL 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 MOV A XY A XY 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 MOV A E HL A E...

Page 298: ...0 1 0 0 0 0 1 1 1 1 1 0 0 ROL E HL C 3E HL 0 C A E HL HL HL 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 ROL E XY C 3E XY 0 C A E XY XY XY 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 ROR sfr CÆ 3sfr0 ÆC A sfr 1 1 0 1 0 0 0 1 1 r7 r6 r5 r4 r3 r2 r1 r0 0 ROR cur CÆ 3cur0 ÆC A cur 1 1 0 1 1 0 0 1 1 r7 r6 r5 r4 r3 r2 r1 r0 0 ROR HL CÆ 3 HL 0 ÆC A HL 1 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 ROR XY CÆ 3 XY 0 ÆC A XY 1 1 ...

Page 299: ...Y A XY 1 XY XY 1 1 1 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 INC E HL E HL A E HL 1 HL HL 1 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 INC E XY E XY A E XY 1 XY XY 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 DEC sfr sfr A sfr 1 1 1 0 1 0 0 0 0 1 r7 r6 r5 r4 r3 r2 r1 r0 0 DEC cur cur A cur 1 1 1 0 1 1 0 0 0 1 r7 r6 r5 r4 r3 r2 r1 r0 0 DEC HL HL A HL 1 1 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 DEC XY XY A XY 1 1 1 0 0 0 0 1 0...

Page 300: ... XY i4 XY A XY i4 1 1 0 0 0 0 0 0 0 1 0 1 1 i3 i2 i1 i0 0 ADD E HL i4 E HL A E HL i4 1 1 0 0 0 0 0 0 0 1 0 0 0 i3 i2 i1 i0 0 ADD E XY i4 E XY A E XY i4 1 1 0 0 0 0 0 0 0 1 0 0 1 i3 i2 i1 i0 0 ADD HL i4 HL A HL i4 HL HL 1 1 1 0 0 0 0 0 0 1 1 0 1 0 i3 i2 i1 i0 0 ADD XY i4 XY A XY i4 XY XY 1 1 1 0 0 0 0 0 0 1 1 0 1 1 i3 i2 i1 i0 0 ADD E HL i4 E HL A E HL i4 HL HL 1 1 1 0 0 0 0 0 0 1 1 0 0 0 i3 i2 i1 ...

Page 301: ...nt XY A C XY XY 1 1 1 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 0 ADCD E HL A E HL A decimal adjustment E HL A C HL HL 1 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 ADCD E XY A E XY A decimal adjustment E XY A C XY XY 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 0 ADCJ cur n cur A n ary adjustment cur C 1 1 0 0 1 0 n2 n1 n0 r7 r6 r5 r4 r3 r2 r1 r0 0 ADCJ HL n HL A n ary adjustment HL C 1 1 0 0 0 0 1 1 0 0 0 1 0 0 n2 n1 n0 0 A...

Page 302: ...0 SUB XY i4 XY A XY i4 1 1 0 0 0 0 0 1 0 1 0 1 1 i3 i2 i1 i0 0 SUB E HL i4 E HL A E HL i4 1 1 0 0 0 0 0 1 0 1 0 0 0 i3 i2 i1 i0 0 SUB E XY i4 E XY A E XY i4 1 1 0 0 0 0 0 1 0 1 0 0 1 i3 i2 i1 i0 0 SUB HL i4 HL A HL i4 HL HL 1 1 1 0 0 0 0 0 1 1 1 0 1 0 i3 i2 i1 i0 0 SUB XY i4 XY A XY i4 XY XY 1 1 1 0 0 0 0 0 1 1 1 0 1 1 i3 i2 i1 i0 0 SUB E HL i4 E HL A E HL i4 HL HL 1 1 1 0 0 0 0 0 1 1 1 0 0 0 i3 i...

Page 303: ...nt XY A C XY XY 1 1 1 0 0 0 0 1 0 1 0 0 1 1 1 1 1 1 0 SBCD E HL A E HL A decimal adjustment E HL A C HL HL 1 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 SBCD E XY A E XY A decimal adjustment E XY A C XY XY 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 SBCJ cur n 1 1 0 0 1 1 n2 n1 n0 r7 r6 r5 r4 r3 r2 r1 r0 0 SBCJ HL n 1 1 0 0 0 0 1 1 0 0 0 1 0 1 n2 n1 n0 0 SBCJ XY n 1 1 0 0 0 0 1 1 0 0 0 1 1 1 n2 n1 n0 0 SBCJ E H...

Page 304: ...0 CMP XY A XY A XY XY 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 CMP E HL A E HL A HL HL 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 CMP E XY A E XY A XY XY 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 CMP cur i4 cur i4 1 1 0 1 0 i3 i2 i1 i0 r7 r6 r5 r4 r3 r2 r1 r0 0 CMP HL i4 HL i4 1 1 0 0 0 0 1 1 0 1 0 1 0 i3 i2 i1 i0 0 CMP XY i4 XY i4 1 1 0 0 0 0 1 1 0 1 0 1 1 i3 i2 i1 i0 0 CMP E HL i4 E HL i4 1 1 0 0 0 0 1 1 0 ...

Page 305: ...2 i1 i0 0 AND XY i4 XY A XY i4 1 1 0 0 0 0 1 0 0 0 1 1 1 i3 i2 i1 i0 0 AND E HL i4 E HL A E HL i4 1 1 0 0 0 0 1 0 0 0 1 0 0 i3 i2 i1 i0 0 AND E XY i4 E XY A E XY i4 1 1 0 0 0 0 1 0 0 0 1 0 1 i3 i2 i1 i0 0 AND HL i4 HL A HL i4 HL HL 1 1 1 0 0 0 0 1 0 1 0 1 1 0 i3 i2 i1 i0 0 AND XY i4 XY A XY i4 XY XY 1 1 1 0 0 0 0 1 0 1 0 1 1 1 i3 i2 i1 i0 0 AND E HL i4 E HL A E HL i4 HL HL 1 1 1 0 0 0 0 1 0 1 0 1 ...

Page 306: ...R HL A HL A HL A 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 XOR XY A XY A XY A 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 XOR E HL A E HL A E HL A 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 XOR E XY A E XY A E XY A 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 XOR HL A HL A HL A HL HL 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 1 0 XOR XY A XY A XY A XY XY 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 0 XOR E HL A E HL A E HL A HL HL 1 1 1 0 0 0 0...

Page 307: ... 0 1 1 1 1 0 1 0 MTST E HL A Testing of all bits in E HL not masked by A HL HL 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 MTST E XY A Testing of all bits in E XY not masked by A XY XY 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 1 MTST cur m Testing of bits in cur not masked by m 1 1 0 1 1 m3 m2 m1 m0 r7 r6 r5 r4 r3 r2 r1 r0 0 MTST HL m Testing of all bits in HL not masked by m 1 1 0 0 0 0 1 0 0 1 0 1 0 m3 m2 m...

Page 308: ...1 1 1 m3 m2 m1 m0 0 MCLR E HL m Clearing of all bits in E HL not masked by m A E HL 1 1 0 0 0 0 1 0 0 0 1 0 0 m3 m2 m1 m0 0 MCLR E XY m Clearing of all bits in E XY not masked by m A E XY 1 1 0 0 0 0 1 0 0 0 1 0 1 m3 m2 m1 m0 0 MCLR HL m Clearing of all bits in HL not masked by m A HL HL HL 1 1 1 0 0 0 0 1 0 1 0 1 1 0 m3 m2 m1 m0 0 MCLR XY m Clearing of all bits in XY not masked by m A XY XY XY 1 ...

Page 309: ... 1 1 1 m3 m2 m1 m0 0 MSET E HL m Setting of all bits in E HL not masked by m A E HL 1 1 0 0 0 0 0 1 0 0 1 0 0 m3 m2 m1 m0 0 MSET E XY m Setting of all bits in E XY not masked by m A E XY 1 1 0 0 0 0 0 1 0 0 1 0 1 m3 m2 m1 m0 0 MSET HL m Setting of all bits in HL not masked by m A HL HL HL 1 1 1 0 0 0 0 0 1 1 0 1 1 0 m3 m2 m1 m0 0 MSET XY m Setting of all bits in XY not masked by m A XY XY XY 1 1 1...

Page 310: ...1 1 m3 m2 m1 m0 0 MNOT E HL m Inverting of all bits in E HL not masked by m A E HL 1 1 0 0 0 0 0 0 0 0 1 0 0 m3 m2 m1 m0 0 MNOT E XY m Inverting of all bits in E XY not masked by m A E XY 1 1 0 0 0 0 0 0 0 0 1 0 1 m3 m2 m1 m0 0 MNOT HL m Inverting of all bits in HL not masked by m A HL HL HL 1 1 1 0 0 0 0 0 0 1 0 1 1 0 m3 m2 m1 m0 0 MNOT XY m Inverting of all bits in XY not masked by m A XY XY XY ...

Page 311: ...1 0 0 0 0 1 0 0 0 1 1 0 n3 n2 n1 n0 0 BCLR XY n XY n 0 A XY 1 1 0 0 0 0 1 0 0 0 1 1 1 n3 n2 n1 n0 0 BCLR E HL n E HL n 0 A E HL 1 1 0 0 0 0 1 0 0 0 1 0 0 n3 n2 n1 n0 0 BCLR E XY n E XY n 0 A E XY 1 1 0 0 0 0 1 0 0 0 1 0 1 n3 n2 n1 n0 0 BCLR HL n HL n 0 A HL HL HL 1 1 1 0 0 0 0 1 0 1 0 1 1 0 n3 n2 n1 n0 0 BCLR XY n XY n 0 A XY XY XY 1 1 1 0 0 0 0 1 0 1 0 1 1 1 n3 n2 n1 n0 0 BCLR E HL n E HL n 0 A E...

Page 312: ...BNOT XY n XY n XY n A XY 1 1 0 0 0 0 0 0 0 0 1 1 1 n3 n2 n1 n0 0 BNOT E HL n E HL n E HL n A E HL 1 1 0 0 0 0 0 0 0 0 1 0 0 n3 n2 n1 n0 0 BNOT E XY n E XY n E XY n A E XY 1 1 0 0 0 0 0 0 0 0 1 0 1 n3 n2 n1 n0 0 BNOT HL n HL n HL n A HL HL HL 1 1 1 0 0 0 0 0 0 1 0 1 1 0 n3 n2 n1 n0 0 BNOT XY n XY n XY n A XY XY XY 1 1 1 0 0 0 0 0 0 1 0 1 1 1 n3 n2 n1 n0 0 BNOT E HL n E HL n E HL n A E HL HL HL 1 1 ...

Page 313: ... 1 0 0 1 0 0 a15 a14 a13 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 MOVHB XY cadr16 XY XY 1 cadr16 15 8 2 3 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 a15 a14 a13 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 MOVHB E HL cadr16 E HL E HL 1 cadr16 15 8 2 3 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 a15 a14 a13 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 MOVHB E XY cadr16 E XY E XY 1 cadr16 15 8 2 3 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 ...

Page 314: ... 0 0 1 0 0 1 0 1 a15 a14 a13 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 MOVLB XY cadr16 XY XY 1 cadr16 7 0 2 3 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 a15 a14 a13 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 MOVLB E HL cadr16 E HL E HL 1 cadr16 7 0 2 3 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 a15 a14 a13 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 MOVLB E XY cadr16 E XY E XY 1 cadr16 7 0 2 3 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1...

Page 315: ...Y XY 2 1 2 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 MOVXB E HL RA E HL E HL 1 RA HL HL 2 1 2 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 MOVXB E XY RA E XY E XY 1 RA XY XY 2 1 2 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 MOVXB RA HL RA HL HL 1 1 3 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 MOVXB RA XY RA XY XY 1 1 3 0 0 0 0 0 1 1 0 0 1 1 0 1 1 1 0 MOVXB RA E HL RA E HL E HL 1 1 3 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 MOVXB RA E XY RA E XY E XY 1...

Page 316: ... 0 0 a15 a14 a13 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 MOVXB E XY xadr16 E XY E XY 1 xadr16 XY XY 2 2 3 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 a15 a14 a13 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 MOVXB xadr16 HL xadr16 HL HL 1 2 3 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 a15 a14 a13 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 MOVXB xadr16 XY xadr16 XY XY 1 2 3 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 a15 a14 a13 a12a11 a1...

Page 317: ... 9 8 7 6 5 4 3 2 1 0 Z C G 0 FCLR G G 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 FCLR C C 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 FCLR Z Z 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 FSET G G 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 FSET C C 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 FSET Z Z 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Jump Instructions 15 INSTRUCTION CODE FLAG MNEMONIC OPERATION W C 14 13 12 11 10 9 8 7 6 5 ...

Page 318: ... Z 1 then PC Next PC radr8 BLE radr8 1 1 0 0 0 0 1 1 1 a7 0 a6 a5 a4 a3 a2 a1 a0 if C 0 Z 0 then PC Next PC radr8 BGT radr8 1 1 0 0 0 0 1 1 1 a7 1 a6 a5 a4 a3 a2 a1 a0 if G 0 then PC Next PC radr8 BNG radr8 1 1 0 0 0 0 1 0 0 a7 0 a6 a5 a4 a3 a2 a1 a0 15 INSTRUCTION CODE FLAG MNEMONIC OPERATION W C 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G LCAL cadr15 2 2 0 a14 a13 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2...

Page 319: ...1 0 RA RA 1 MOV CBR i4 1 1 0 0 0 0 0 0 0 0 0 0 1 1 i3 i2 i1 i0 CBR i4 MOV EBR i4 1 1 0 0 0 0 0 0 0 0 0 0 1 0 i3 i2 i1 i0 EBR i4 MOV RA0 i4 1 1 0 0 0 0 0 0 1 0 0 0 0 0 i3 i2 i1 i0 RA0 i4 MOV RA1 i4 1 1 0 0 0 0 0 0 1 0 0 0 0 1 i3 i2 i1 i0 RA1 i4 MOV RA2 i4 1 1 0 0 0 0 0 0 1 0 0 0 1 0 i3 i2 i1 i0 RA2 i4 MOV RA3 i4 1 1 0 0 0 0 0 0 1 0 0 0 1 1 i3 i2 i1 i0 RA3 i4 MOV H i4 1 1 0 0 0 0 0 0 0 1 0 0 1 1 i3 ...

Page 320: ...emory area Mask option area for ML63326 address 5FE0H ML63326 Mask Option Data Assignment Format Example of mask option data generation When the crystal oscillation circuit is specified for the low speed clock oscillation circuit ORG 5FE0H Useanassemblerpseudo instructiontosettheaddressofoptiondata to 5FE0H DW 0 Low speed oscillation clock crystal oscillation When the RC oscillation circuit is spe...

Page 321: ...Appendix 60 ML63326 User s Manual Appendix G ...

Page 322: ...ML63326 User s Manual First Edition June 1999 Second Edition September 1999 1999 Oki Electric Industry Co Ltd PEUL63326 02 ...

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