Chapter 1 System Overview
RHINO 5 User’s Manual
5
1.2
Central Processing Unit
The Pentium processor is a superscalar, pipelined CPU that
provides next generation performance for the existing PC
compatible software.
The processor is equipped with an 8K code cache and an 8K
data cache . Each cache is organized in a 2-way set-associative
architecture, offering higher hit rates. The data cache can be
configured in write-back or write-through modes.
The internal numeric coprocessor is redesigned to give three
times the performance of the 80486 FPU. It is backward
compatible with i486DX math coprocessor and complying to
ANSI/IEEE standard 754-1985.
1.3
External Cache Subsystem
The external cache of RHINO 5 is organized in a direct-mapped
configuration with sizes of 256KB, or 512KB or 1MB. It can
operate in write-through mode or write-back mode
.
Either 3.3V asynchronous SRAM or mixed mode voltage
asynchronous SRAM can be used in RHINO 5.
1.4
DRAM Subsystem
The main memory in RHINO 5 is organized as a 64-bit memory
pool. Both fast-page mode and EDO DRAMs are supported.
EDO DRAM stands for Extended Data Out DRAM and is
designed to improve the DRAM read performance. EDO
DRAM holds the memory data valid until the next CAS# falling
edge, unlike standard fast page mode DRAM which tri-states
the memory data when CAS# is deasserted to precharge for the
next cycle. As a result, the CAS# precharge can now overlap
