Octek DRAGON EISA 486, Manual

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GENERAL FEATURES
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continue to execute program out of the cache while the
other bus master occupying the DRAM. Alternately, a
cache memory reduces the CPU's utilisation onto the
DRAM. The CPU is only put into wait state when it has to
utilize the DRAM to exchange information between the
cache and DRAM while other bus master is using it. This
should be quite rare in a system having a good external
cache memory design to minimize CPU utilisation onto
DRAM. Thus, a cache memory can effective decouple
the CPU from the rest of bus master. The higher the hit
rate, the better the write policy, the smaller the read
miss penalty, the better is the decoupling effect.
The external cache of the DRAGON EISA board
adopt a write back design. In a cache based system,
when CPU perform a write operation, the content of
cache would be different from that of DRAM if the
operation is only perform to the cache. The cache
content is said to be stalled. In some system, the CPU
write operation is performed simultaneously to the DRAM
as well as to the cache. Such write policy is termed as
write-through and the performance of write operation is
limited by the slow DRAM. In some system, the CPU
write is performed to the cache as well as a buffer in the
DRAM subsystem. The speed of the write operation is
not limited to DRAM. Such design is called post-write.
However, post-write cache design can only buffer a
single write. If CPU perform more write operation before
the buffered data has been stored onto DRAM, CPU is
still put into wait states. In other systems, the DRAM
subsystem has included several buffers to hold more
continuous write operations. In a write-back cache
design, CPU is performed only to the cache so that write
operation is completed in the fastest manner. Data in
cache is referred as dirty as soon as it is written by CPU.
The dirty data is only put back to DRAM when the same
cache location have to be re-used by a later read miss,
by which new data is read from DRAM and stored in the
cache.
Write-back design provide best write performance
and lowest DRAM utilisation because CPU write data is