2002 Nov 22
42
NXP Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
Notes
1. All supply pins V
DD
and V
SS
must be connected to the same external power supply unit.
2. When the DAC must drive a higher capacitive load (above 50 pF), a series resistor of 100
Ω
must be used to prevent
oscillations in the output stage of the operational amplifier.
3. The output voltage of the DAC is proportional to the DAC power supply voltage.
Digital inputs
V
IH
HIGH-level input voltage
0.8V
DDD
−
V
DDD
+ 0.5 V
V
IL
LOW-level input voltage
−
0.5
−
+0.2V
DDD
V
⎪
I
LI
⎪
input leakage current
−
−
10
μ
A
C
i
input capacitance
−
−
10
pF
R
pu(int)
internal pull-up resistance
16
33
78
k
Ω
R
pd(int)
internal pull-down resistance
16
33
78
k
Ω
Digital outputs
V
OH
HIGH-level output voltage
I
OH
=
−
2 mA
0.85V
DDD
−
−
V
V
OL
LOW-level output voltage
I
OL
= 2 mA
−
−
0.4
V
I
O(max)
maximum output current
−
3
−
mA
Digital-to-analog converter;
note 2
V
o(rms)
output voltage (RMS value)
f
i
= 1.0 kHz tone at
0 dBFS; note 3
850
900
950
mV
Δ
V
o
unbalance of output voltages
f
i
= 1.0 kHz tone
−
0.1
0.4
dB
V
ref
reference voltage
measured with respect to
V
SSA
0.45V
DDA
0.50V
DDA
0.55V
DDA
V
(THD+N)/S
total harmonic
distortion-plus-noise to signal
ratio
f
i
= 1.0 kHz tone
at 0 dBFS
−
−
82
−
77
dB
at
−
40 dBFS; A-weighted
−
−
60
−
52
dB
S/N
signal-to-noise ratio
f
i
= 1.0 kHz tone; code = 0;
A-weighted
95
100
−
dB
α
cs
channel separation
f
i
= 1.0 kHz tone
−
110
−
dB
SPDIF input
V
i(p-p)
AC input voltage
(peak-to-peak value)
0.2
0.5
3.3
V
R
i
input resistance
−
6
−
k
Ω
V
hys
hysteresis voltage
−
40
−
mV
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
