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NXP Semiconductors SJA1105SMBEVM User Manual Download Page 10

 

 

NXP Semiconductors 

AH1721 

 

SJA1105SMBEVM UM 

AH1721 

All information provided in this document is subject to legal disclaimers. 

© NXP Semiconductors N.V. 2018. All rights reserved. 

User Manual 

Rev. 1.00 

— 16 July 2018 

10 of 35 

LED label  Color 

Description: 

P2-L,  

P2-R, 

P3-L, 

P3-R 

L=green 

R=yellow 

LEDs integrated in the GBit connectors P2 and P3 
L is controlled by the GBit PHY’s LED2 output, and R by the LED1 
output. In Tri-Color dual-LED mode the following settings are used: 

state 

L = green 

R = yellow 

Link off 

off 

off 

1000 Link, no activity 

on 

off 

1000 Link/Activity (RX, TX) 

blink 

off 

100 Link, no activity 

off 

on 

100 Link/Activity (RX, TX) 

off 

blink 

10 Link, no activity 

on 

on 

10 Link/Activity (RX, TX) 

blink 

blink 

 

D6, D7, 
D8 

green 

Power-Good LEDs for the voltages generated by switching regulators. 

D6 = 5V0 

D7 = 3V3 

D8 = 2V5 

D11, D12 

green 

Power-Good LEDs for the voltages generated by LDOs. 

D11 = 1V8 

D12 = 1V2 

D3 

green 

Labeled “ALIVE”. General purpose LED connected to the uC. Used by 
the 

μC software as a heartbeat. This LED should continuously blink if 

the example SW is running.  

D17 

green 

General purpose LED connected to the uC. No special meaning. 

D13 

green 

PTP LED. The LED is connected to SwitchA’s PTP_CLK output by a 
transistor inverter. If PTP_CLK is low, the LED is off. 

Positions of the LEDs are shown in Fig 4. 

4.8  Jumper blocks and connectors 

The position of the jumper blocks and connectors is shown in Fig 4. 

Table 4. 

Jumper blocks and connectors  

Name 

Meaning/Usage 

J1 

Power Jack 12V input 

J2 

USB Type B receptacle for the serial link to PC 

J3,J5 

CAN bus termination setting; J3 = CAN_L, J5 = CAN_H 

1-2: 120R termination active (used for an end node on the CAN bus) 

2-3: 2k6 termination active (used for a middle node on the CAN bus) 

No jumper: No termination 

J4 

Fast Ethernet RJ45 receptacle with LEDs 

J6 

Jumper block for selecting the source of the enable signal VREG_EN to the 
switching power regulators (5V0, 3V3, 2V5)  

2-3: 12V0 

– regulators permanently enabled 

1-2: VREG_EN is under control of the PHYs and the processor 

– see ch 6.3 for 

sleep/wakeup 

Summary of Contents for SJA1105SMBEVM

Page 1: ...1 00 16 July 2018 User Manual Document information Info Content Keywords SJA1105PQRS SJA1105S SJA1105S Evaluation Board SJA1105SMBEVM Cascading Ethernet Wakeup Sleep Abstract The SJA1105SMBEVM Evaluation Board is described in this document ...

Page 2: ...disclaimers NXP Semiconductors N V 2018 All rights reserved User Manual Rev 1 00 16 July 2018 2 of 35 Contact information For more information please visit http www nxp com For sales office addresses please send an email to mailto salesaddresses nxp com Revision history Rev Date Description 1 00 20180716 Release ...

Page 3: ...ke a X to Ethernet gateway communication hub etc Fig 1 SJA1105SMBEVM board This user manual describes the board hardware and the software development environment to allow the user to quickly bring up a working system and to pave the way towards an own customized software and in the end towards an all custom system After the HW description the manual walks the user through the process to create the...

Page 4: ...valuation Board Software Package TJA1145FD CAN Transceiver Product data sheet and Application Hint AH1309 MPC5748G reference manual If you want to download and run SW on the SJA1105SMBEVM you also need a JTAG Debug adapter The easiest solution is the PEMicro USB Multilink Universal USB to JTAG debug probe http www pemicro com products product_viewDetails cfm product_id 15320168 as this is already ...

Page 5: ...Block diagram indicating the primary functional blocks and interconnections The primary functional components of the SJA1105SMBEVM Evaluation Module are 1 Microcontroller MPC5748G 2 switches SJA1105S ETH SW A and ETH SW B 3 100BASE T1 PHYs ETH PHY TJA1102 2 TJA1102S 2 1000BASE T PHYs 1G PHY KSZ9031 1 100BASE TX PHY FE PHY DP83848C 1 CAN Transceiver TJA1145FD 1 UART USB Converter FT230XQ The main E...

Page 6: ... and depends on the number of active PHYs and if the port is connected to a peer The power supply topology is shown in Fig 3 The switching regulators for 5V0 3V3 and 2V5 are controlled by the signal VREG_EN which can be either fixed to enable or controlled by a combination of an output signal from the PHYs and some sign off signal from the CPU The selection is done with a jumper J6 With this schem...

Page 7: ... SJA1105S Yes Yes The SJA1105S s fifth port is a SGMII only port and is capable to operate at up to 1Gbps The other four ports can be individually configured to operate at 10Mbps 100Mbps or 1Gbps depending on the capability and configuration of the PHY connected Interfacing a PHY to one of these four ports can be done using one of the 3 supported MII interface standards MII RMII or RGMII This port...

Page 8: ... mode Connector SMI address Master Slave Switch A0 Proc Port0 MII Lite Switch A1 U19 TJA1102S RMII J11 4 Master Switch A2 U18 KSZ9031 RGMII P2 2 Switch A3 U17 KSZ9031 RGMII P1 3 Switch A4 Switch B4 SGMII Switch B0 U21A TJA1102 RMII J14 6 Master Switch B1 U21B TJA1102 RMII J15 7 Master Switch B2 U20A TJA1102 RMII J12 8 Master Switch B3 U20B TJA1102 RMII J13 9 Master Switch B4 Switch A4 SGMII Proc P...

Page 9: ...ive D2 D4 D5 D15 D16 green link up indication LEDs for the 100BASE T1 ethernet ports Each LED is controlled by the on board uC and is set cleared by the LinkUp LinkFail interrupt of the associated port s PHY D2 Port A1 D4 Port B0 D5 Port B1 D15 Port B2 D16 Port B3 J4 L J4 R L green R yellow LEDs integrated in the FE connector J4 L Link controlled by the FE PHY U10 LEDLINK output By default Mode 1 ...

Page 10: ...eral purpose LED connected to the uC Used by the μC software as a heartbeat This LED should continuously blink if the example SW is running D17 green General purpose LED connected to the uC No special meaning D13 green PTP LED The LED is connected to SwitchA s PTP_CLK output by a transistor inverter If PTP_CLK is low the LED is off Positions of the LEDs are shown in Fig 4 4 8 Jumper blocks and con...

Page 11: ...FTDI FT231X1 It is included on the board to provide an easy serial interface between a host computer and the μC The example SW project uses this interface for a debug console with 115200 8N1 and no HW handshaking protocol Use TeraTerm or any other terminal emulation software for accessing the console To access the µC s UART via USB under Windows a device driver from FTDI must be installed This dev...

Page 12: ...switch with 16 positions The software can make use of the rotary switch to select a specific board configuration The example software project uses the rotary settings in the following way to enable disable ethernet and or CAN operation Table 7 Rotary switch configuration in the example project Configuration Ethernet operation CAN operation 0 no no 1 yes yes 2 yes no 3 no yes 4 F Not used see confi...

Page 13: ...or Power Architecture home page is at https www nxp com support developer resources run time software s32 design studio ide s32 design studio ide for power architecture based mcus S32DS PA At the time of writing this document you need the basic packet S32 Design Studio for Power Architecture 2017 R1 Windows Linux and the cumulative update S32 Design Studio for Power Architecture 2017 R1 Update 2 M...

Page 14: ...p This can be done either Online S32DS Eclipse downloads the package itself and installs it then This requires that Eclipse can access the internet which is often not possible due to corporate firewall rules and proxy architectures Web browsers are usually capable to deal with these topics but for other SW this is cumbersome Offline the update package is downloaded with the web browser and tempora...

Page 15: ...isclaimers NXP Semiconductors N V 2018 All rights reserved User Manual Rev 1 00 16 July 2018 15 of 35 2 Click Add Fig 7 S32DS installing SDK update step 2 3 Click Archive and select the zip file with the update patch downloaded earlier and stored in the filesystem Click OK Fig 8 S32DS installing SDK update step 3 ...

Page 16: ...e your workspace usually just an empty directory in the user s part of the file system Start S32 Design Studio for Power Architecture and select this workspace You will see an empty Project Explorer pane usually upper left corner Create an empty project with File New Project not C Project not Project from Example just pure Project and choose a wizard with General Project Use a project name for exa...

Page 17: ...asterbitsPerFrame Type specification is not defined typedspi_bitsperframe_t symbol MasterPCS Error Unknown type info typedspi_bitsperframe_t in item Bits frame MasterbitsPerFrame from component dspi Error Unknown type info typedspi_bitsperframe_t in item PCS MasterPCS from component dspi Error Unknown type info typedspi_bitsperframe_t in item Bits frame SlavebitsPerFrame from component dspi Error ...

Page 18: ... executable If all goes well you will have a elf file which can be downloaded and started on the target board with a JTAG debugger like PEMicro ML universal or with the Lauterbach debugger 5 3 Download and run the firmware The following description presumes that the PEMicro ML Universal probe is used Call Run DebugConfigurations also available under the beetle symbol and check the entries in the c...

Page 19: ... Fig 11 Screenshot of the debug configuration popup window part1 If you have chosen the recommended project name sja1105smbevm_example ch 5 2 you will see a predefined debug configuration under GDB PEMicro Interface Debugging else you must add some items for your debug configuration in the main and debugger pane Refer to Fig 12 and Fig 13 for details Fig 12 Screenshot of the debug configuration po...

Page 20: ... can see the actions behind the scenes on the console window Usually this involves connecting to the GDB server in the debug probe erasing the flash downloading and writing the program image to the flash and starting the downloaded image If everything went well you will see the debug view a combination of windows and sub windows well adapted for debugging and the main window will show that the pro...

Page 21: ... SJA1105SMBEVM UM AH1721 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2018 All rights reserved User Manual Rev 1 00 16 July 2018 21 of 35 Fig 14 Screenshot of a debug session ...

Page 22: ...nk speed only This is since the switches MACs only allow full duplex links o The uC periodically sends out data packets on its ENET0 connected to the switch and ENET1 FE ports As the chosen destination address 08 00 27 02 12 88 is not known in the switch s L2 address tables the packets are flooded to all ports The µC uses 08 00 27 02 12 01 and 08 00 27 02 12 02 as source address These addresses ar...

Page 23: ...ents are connected to peripherals in the µC which are for example implementing a communication interface UART SPI xMII SMI etc or simply GPIOs For simplicity the GPIOs are not drawn in Fig 15 but they control LEDs reset and enable lines of those on board HW components The uC ENET peripheral has an MII Lite Interface for ethernet data but also a SMI interface for accessing the PHYs The next upper l...

Page 24: ...e configuration is done interactively within the Eclipse framework The default settings may be perused and changed if needed The SDK s API documentation is available in the html tree starting at the SDK installation folder in C NXP S32DS_Power_v2017 R1 S32DS S32_SDK_MPC574xx_BETA_0 9 0 doc A list of the device driver calls is provided within the Eclipse framework in the ProcessorExpert s Component...

Page 25: ... or when data has been received or transmitted Callback functions are called in the context of a device specific service task or from the interrupt context Therefore they should not perform time or stack consuming operations In the example project the ENET callback functions handle receiving ethernet packets The PHY callbacks are for handling link detection changes and for auto negotiation result ...

Page 26: ...DK module there are c and h files containing data structure definitions configuration data arrays array dimensions and more definitions in a form usable for the SDK device driver The data structures must be passed to the driver s initialization function ProjectSettings essential files for producing an executable like linker files memory layout and processor specific generic low level files like st...

Page 27: ...ific modules in sja1105smbevm the application modules and main c Debug_FLASH and or Debug_RAM are directories which contain everything what the S32DS tools create during the project build phase depending on which build configuration is active Project_Settings is a directory with links to the SDK installation directory 6 3 Changing the static switch configuration stream Creating a new configuration...

Page 28: ...ple project firmware a more elaborate example example and an example making use of the TSN features like CBS policer MAC filtering for gPTP etc in example_TSN There are also some two examples snake1 and snake2 which are identical to simple except they implement snake like paths through the switches using loopback cables They can be used for testing purposes 3 Create a copy of one of the example co...

Page 29: ...cated 7 Execute the batch script A new version of NXP_SJA1105P_configStream c is created overwriting the old one 8 Rebuild the project 6 4 Wakeup and Sleep The SJA1105SMBEVM hardware allows applications to send the board to sleep mode and to get woken up either by a remote wakeup command received over one of the communication links or by a local event represented by a pushbutton A simplified schem...

Page 30: ...or wakeup sleep or for debugging or for the first bring up of the board Waking the board may be triggered by a remote wakeup command received by one of the PHYs Once the PHY detects the remote wakeup request it puts the INH high again which effectively switches on power again and starts the boot process Depending on the PHY configuration before being sent to sleep the PHY may be configured to also...

Page 31: ... Freescale now NXP standard for a debugging interface to embedded microcontrollers PHY Physical layer or chip responsible for adapting to the physical layer of a communication link RMII Reduced Media Independent Interface RGMII Reduced Gigabit Media Independent Interface S32DS Eclipse based development environment for NXP microcontroller S32 Design Studio SDK Software developer kit set of librarie...

Page 32: ...le responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept...

Page 33: ...6 S32DS installing SDK update step 1 14 Fig 7 S32DS installing SDK update step 2 15 Fig 8 S32DS installing SDK update step 3 15 Fig 9 S32DS installing SDK update step 4 16 Fig 10 Screenshot of a successfully created executable 18 Fig 11 Screenshot of the debug configuration popup window part1 19 Fig 12 Screenshot of the debug configuration popup window part2 19 Fig 13 Screenshot of the debug confi...

Page 34: ...Rev 1 00 16 July 2018 34 of 35 10 List of tables Table 1 SJA1105P Q R S variants 7 Table 2 Ethernet port usage and default PHY configurations 8 Table 3 SJA1105SMBEVM LEDs overview 9 Table 4 Jumper blocks and connectors 10 Table 5 Pinning of the debug connector J10 12 Table 6 Buttons and switches 12 Table 7 Rotary switch configuration in the example project 12 Table 8 Abbreviations 30 ...

Page 35: ...8 4 7 LEDs 9 4 8 Jumper blocks and connectors 10 4 8 1 USB connector 11 4 8 2 Software debug connector 11 4 9 Buttons and switches 12 5 Getting started 12 5 1 Install S32DS 13 5 2 Import example project files and build an executable file 16 5 3 Download and run the firmware 18 5 4 Example Software features 22 6 Example project software 23 6 1 Components and Layers 23 6 2 Code organization 25 6 3 C...

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