EXTERNAL USE
21
S32R274RRUEVB: Communication Interfaces
2 of 2
Ethernet
Ethernet
DESCRIPTION
PORT
RGMII_TXCLK
PG11
RGMII_TX_D0
PD0
RGMII_TX_D1
PD3
RGMII_TX_D2
PD4
RGMII_TX_D3
PG10
RGMII_TX_EN
PC15
RGMII_RX_CLK
PH13
RGMII_RX_D0
PD5
RGMII_RX_D1
PD6
RGMII_RX_D2
PH4
RGMII_RX_D3
PH5
RGMII_RX_DV
PD2
RESET_B*
RESET_B
ENET_REF_CLK
PI2
MDC
PG9
MDIO
PG8
MIPI-CSI2
MIPI-CSI2
DESCRIPTION
PORT
ETIMER2_ETC3
PC12
SD_0_ADCN*
SDADC0 Neg. Inp.
SD_0_ADCP*
SDADC0 Pos. Inp.
CTE_RFS
PE13
DSPI2_SOUT
PA12
DSPI2_SIN
PA13
DSPI2_CS0
PA10
DSPI2_SCK
PA11
SIUL_EIRQ5
PA5
MCU_CLK_P*
XOSC_XTAL (DNP)
MCU_CLK_N*
XOSC_EXTAL (DNP)
ETIMER2_ETC0
PB2
MCU_CLK_SE*
XOSC_EXTAL (DNP)
ADC0_AN_0
PB7
RESET_B*
RESET_B
CTE_RCS
PF0
CSI_LANE2N*
Lane2 Neg. Inp.
CSI_LANE2P*
Lane2 Pos. Inp.
CSI_LANE0P*
Lane0 Neg. Inp.
CSI_LANE0N*
Lane0 Pos. Inp.
CSI_CLKN*
Clock Neg. Inp.
CSI_CLKP*
Clock Pos. Inp.
CSI_LANE1P*
Lane1 Pos. Inp.
CSI_LANE1N*
Lane1 Neg. Inp.
CSI_LANE3N*
Lane3 Neg. Inp.
CSI_LANE3P*
Lane3 Pos. Inp.
*These pins map to special purpose pads on the S32R274 MCU instead of general purpose
ports as controlled by the SIUL module. Information for these can be found under “Misc Pins” of
“S32R274_IO_Signal_Description_and_Input_multiplexing_tables_Rev
n
.xlsx”.
Summary of Contents for S32R274RRUEVB
Page 25: ...EXTERNAL USE 24 Package Level Pinout Diagram S32R274 257 BGA ...
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