NXP Semiconductors PXN2020, Reference Manual, Page: 648 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-34 Freescale Semiconductor
26.5.2.21 Protocol Status Register 2 (PSR2)
This register provides a snapshot of status information about the Network Idle Time NIT, the Symbol
Window and the clock synchronization. The NIT related status bits NBVB, NSEB, NBVA, and NSEA are
updated by the controller after the end of the NIT and before the end of the first slot of the next
communication cycle. The Symbol Window related status bits STCB, SBVB, SSEB, MTB, STCA, SBVA,
SSEB, and MTA are updated by the controller after the end of the symbol window and before the end of
the current communication cycle. If no symbol window is configured, the symbol window related status
bits remain in their reset state. The clock synchronization related CLKCORRFAILCNT is updated by the
controller after the end of the static segment and before the end of the current communication cycle.
REMCSAT Remaining Coldstart Attempts — protocol related variable: vRemainingColdstartAttempts
This field provides the number of remaining cold start attempts that the controller will execute.
CPN Leading Cold Start Path Noise — protocol related variable: vPOC!ColdstartNoise
This status bit is set if the controller has reached the POC:normal active state via the leading cold start path
under noise conditions. This indicates there was some activity on the FlexRay bus while the controller was
starting up the cluster.
0 No such event.
1
POC:normal active state was reached from POC:startup state via noisy leading cold start path.
HHR Host Halt Request Pending — protocol related variable: vPOC!CHIHaltRequest
This status bit is set when controller receives the HALT command from the application via the Protocol Operation
Control Register (POCR) . The controller clears this status bit after a hard reset condition or when the protocol
is in the POC:default config state.
0 No such event.
1 HALT command received.
FRZ Freeze Occurred — protocol related variable: vPOC!Freeze
This status bit is set when the controller has reached the POC:halt state due to the host FREEZE command or
due to an internal error condition requiring immediate halt. The controller clears this status bit after a hard reset
condition or when the protocol is in the
POC:default config state.
0 No such event.
1 Immediate halt due to FREEZE or internal error condition.
APTAC Allow Passive to Active Counter — protocol related variable: vPOC!vAllowPassivetoActive
This field provides the number of consecutive even/odd communication cycle pairs that have passed with valid
rate and offset correction terms, but the protocol is still in the
POC:normal passive state due to an application
configured delay to enter POC:normal active state. This delay is defined by the allow_passive_to_active field in
the Protocol Configuration Register 12 (PCR12) .
Base + 0x002C Additional Reset: RUN Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R NBVB NSEB STCB SBVB SSEB MTB NBVA NSEA STCA SBVA SSEA MTA CLKCORRFAILCNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-21. Protocol Status Register 2 (PSR2)
Table 26-26. PSR1 Field Descriptions (continued)
Field Description