NXP Semiconductors PXN2020, Reference Manual, Page: 626 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-12 Freescale Semiconductor
26.5.2.1 Register Reset
All registers except the Message Buffer Cycle Counter Filter Registers (MBCCFRn) , Message Buffer
Frame ID Registers (MBFIDRn) , and Message Buffer Index Registers (MBIDXRn) are reset to their reset
value on system reset. The registers mentioned above are located in physical memory blocks and, thus,
they are not affected by reset. For some register fields, additional reset conditions exist. These additional
reset conditions are mentioned in the detailed description of the register. The additional reset conditions
are explained in
Table 26-5 .
26.5.2.2 Register Write Access
This section describes the write access restriction terms that apply to all registers.
26.5.2.2.1 Register Write Access Restriction
For each register bit and register field, the write access conditions are specified in the detailed register
description. A description of the write access conditions is given in
Table 26-6 . If, for a specific register
bit or field, none of the given write access conditions is fulfilled, any write attempt to this register bit or
field is ignored without any notification. The values of the bits or fields are not changed. The condition
term [A or B] indicates that the register or field can be written to if at least one of the conditions is fulfilled.
Table 26-4. Register Access Conventions
Convention Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writeable.
R* Reserved bit or field, will not be changed. Application must not write any value different from the reset value.
FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
rwm A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c Write one to clear. A flag bit that can be read, is cleared by writing a one, writing 0 has no effect.
Reset Value
0 Resets to zero.
1 Resets to one.
– Not defined after reset and not affected by reset.
Table 26-5. Additional Register Reset Conditions
Condition Description
Protocol RUN Command The register field is reset when the application writes to RUN command “0101” to the
POCCMD field in the
Protocol Operation Control Register (POCR) .
Message Buffer Disable The register field is reset when the application has disabled the message buffer.
This happens when the application writes 1 to the message buffer disable trigger bit
MBCCSRn[EDT] while the message buffer is enabled (MBCCSRn[EDS] = 1) and the
controller grants the disable to the application by clearing the MBCCSRn[EDS] bit.