NXP Semiconductors PXN2020, Reference Manual, Page: 490 / 1376

System Timer Module (STM)
PXN20 Microcontroller Reference Manual, Rev. 1
21-2 Freescale Semiconductor
21.3 Memory Map and Register Definition
The STM has 14 32-bit read and write access registers. The STM registers can only be accessed using
32-bit (word) accesses. Attempted references using a different size or to a reserved address generates a bus
error termination.
21.3.1 Memory Map
The STM memory map is shown in Table 21-1 .
21.3.2 Register Descriptions
The following sections detail the individual registers within the STM.
Table 21-1. STM Memory Map
Offset from
STM_BASE
(0xFFF3_C000)
Register Access
Reset
Value
1
1
See register definition.
Section/Page
0x0000 STM_CR – STM Control Register R/W 0x0000_0000 21.3.2.1/21-3
0x0004 STM_CNT – STM Counter Value R/W 0x0000_0000 21.3.2.2/21-3
0x0008–0x000F Reserved
0x0010 STM_CCR0 – STM Channel 0 Control Register R/W 0x0000_0000 21.3.2.3/21-4
0x0014 STM_CIR0 – STM Channel 0 Interrupt Register R/W 0x0000_0000 21.3.2.4/21-4
0x0018 STM_CMP0 – STM Channel 0 Compare Register R/W 0x0000_0000 21.3.2.5/21-5
0x001C Reserved
0x0020 STM_CCR1 – STM Channel 1 Control Register R/W 0x0000_0000 21.3.2.3/21-4
0x0024 STM_CIR1 – STM Channel 1 Interrupt Register R/W 0x0000_0000 21.3.2.4/21-4
0x0028 STM_CMP1 – STM Channel 1 Compare Register R/W 0x0000_0000 21.3.2.5/21-5
0x002C Reserved
0x0030 STM_CCR2 – STM Channel 2 Control Register R/W 0x0000_0000 21.3.2.3/21-4
0x0034 STM_CIR2 – STM Channel 2 Interrupt Register R/W 0x0000_0000 21.3.2.4/21-4
0x0038 STM_CMP2 – STM Channel 2 Compare Register R/W 0x0000_0000 21.3.2.5/21-5
0x003C Reserved
0x0040 STM_CCR3 – STM Channel 3 Control Register R/W 0x0000_0000 21.3.2.3/21-4
0x0044 STM_CIR3 – STM Channel 3 Interrupt Register R/W 0x0000_0000 21.3.2.4/21-4
0x0048 STM_CMP3 – STM Channel 3 Compare Register R/W 0x0000_0000 21.3.2.5/21-5
0x004C–0x3FFF Reserved