NXP Semiconductors PXN2020, Reference Manual, Page: 491 / 1376

System Timer Module (STM)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 21-3
21.3.2.1 STM Control Register (STM_CR)
The STM Control Register (STM_CR) includes the prescale value, freeze control, and timer enable bits.
21.3.2.2 STM Count Register (STM_CNT)
The STM Count Register (STM_CNT) holds the timer count value.
Offset: ST 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CPS
0 0 0 0 0 0
FRZ TEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-1. STM Control Register (STM_CR)
Table 21-2. STM_CR Field Descriptions
Field Description
CPS Counter Prescaler. Selects the clock divide value for the prescaler (1–256).
0x00 Divide system clock by 1.
0x01 Divide system clock by 2.
...
0xFF Divide system clock by 256.
FRZ Freeze. Allows the timer counter to be stopped when the device enters debug mode.
0 STM counter continues to run in debug mode.
1 STM counter is stopped in debug mode.
TEN Timer Counter Enabled.
0 Counter is disabled.
1 Counter is enabled.
Offset ST 0x0004 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-2. STM Count Register (STM_CNT)
Table 21-3. STM_CNT Field Descriptions
Field Description
CNT Timer count value used as the time base for all channels. When enabled, the counter increments at the rate of the
system clock divided by the prescale value.