NXP Semiconductors PT2001 Page 68 Programming Manual And Instruction Set Download

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NXP Semiconductors

PT2001SWUG

PT2001 programming guide and instruction set

PT2001SWUG

All information provided in this document is subject to legal disclaimers.

User guide

Rev. 3.0 — 29 April 2019

68 / 153

jsrf

Description:

Configures the jump to absolute location on status register condition.
If the condition defined by the SrSel operand is satisfied according to the polarity Pol, the

program counter (uPC) is handled such as the next executed instruction is located into

the destination address contained in one of the jump registers.
The destination address defined by the op1 register is any of the absolute Code RAM

location.

Assembler syntax:

jsrf op1 SrSel Pol;

Operands:
•

op1 – One of the registers listed in the operand

Section 3.1.4 "JpReg subset"

•

SrSel – Operand defines the status register condition (Status_reg_uc0 (105h, 125h)

and Status_reg_uc1 (106h, 126h)) that triggers the jump

Operand label

Operand description

Status register bit 0 (LSB)

Status register bit 1

Status register bit 2

Status register bit 3

Status register bit 4

Status register bit 5

Status register bit 6

Status register bit 7

Status register bit 8

Status register bit 9

b10

Status register bit 10

b11

Status register bit 11

b12

Status register bit 12

b13

Status register bit 13

b14

Status register bit 14

b15

Status register bit 15 (MSB)

Pol – Operand defines the active polarity for the selected bit

Operand label

Operand description

low

Active condition if the selected bit is '0'

high

Active condition if the selected bit is '1'

Summary of Contents for PT2001

Page 1: ...the CRAM Relative address relative The relative address parameter is represented by 5 bits The physical address of the destination is obtained by adding the relative address to the physical address of the instruction that uses the parameter that is the value of the uprogram counter when the instruction is executed The relative address must be considered as two s complement represented and must be ...

Page 2: ...ister 3 General Purpose Register 4 Immediate Register Multiplication Results MSBs GPR6 ALU Condition Register Multiplication Results LSBs GPR7 Figure 1 ALU block diagram These operations consume the operand While the ALU is busy performing an operation request of other operations is impossible In such cases the request is ignored by the ALU The ALU instructions are Addition add addition with immed...

Page 3: ...N Addition or subtraction sign result 4 UNSIGNED_UND Unsigned underflow 3 UNSIGNED_OVR Unsigned overflow 2 SIGNED_UND Signed underflow 1 SIGNED_OVR Signed overflow 0 OP_DONE Operation complete SHIFT_OUT is the last bit shifted out either left or right from a shift operation CONV_SIGN is the product of all signs removed by toint instruction This bit can be reset by performing a toint conversion wit...

Page 4: ...de an anti glitch functionality in order to reject glitches on the input start signal and also to provide the gen_start_uc0 gen_start_uc1 start_latch_uc0 and start_latch_uc1 signals The main purpose of this block is to generate the internal gen_start signals feeding the microcores starting from the startx pins Each microcore can be sensitive to the 6 startx pins according to the sensitivity map de...

Page 5: ...10 bit counter used to address the Code RAM containing the microprogram After the Code RAM is locked this counter is loaded with an entry point selected through a SPI register refer to the Uc0_entry_point 10Ah and 12Ah and the Uc1_entry_point 10Bh and 12Bh sections which is the address of the first active instruction If an interrupt is requested the uPC counter is moved to the appropriate interrup...

Page 6: ... configured inside the six row wait table terminal_counts any of the four terminal count tc1 tc2 tc3 and tc4 signals can be checked to detect if any of the four counters has reached its end of count position Flags checks the value both polarities of one of the 16 flag signals available Shortcut feedback the voltage feedback both polarities related to the three shortcut outputs gen_start checks the...

Page 7: ...hecked by the jump instructions are the same as the wait instruction with the addition of the following inputs ctrl_reg checks the value both polarities of one of the 16 control bits available in the ctrl_reg register see register 101h 102h 121h 122h status_bits checks the value both polarities of one of the 16 control bits available in the Status_bits register see register 105h 106h 125h 126h vol...

Page 8: ...ed to load and store data memory These instructions also set the access mode which can be set to either Immediate _ofs parameter to be used mode or Indexed mode using the slab instruction Indexed mode is when an offset from the Base Address register is applied to the access s address ofs parameter to be used It is possible to modify the value of add_base with the stab instruction aaa 028740 Regist...

Page 9: ...LU registers and place the result in one of the ALU registers addi Add an ALU register to the value in the immediate register and place the result in an ALU register mul Multiply two ALU registers and place the result in reg32 muli Multiply an ALU register with the value in the immediate register and place the result in reg32 stal Set arithmetic logic mode sub Subtract two ALU registers and place ...

Page 10: ...ft right multiplication result register sh32ri Shift right multiplication result register by immediate value shl Shift left ALU register shl8 Shift left ALU register by 8 bits shli Shift left the ALU register by immediate value shls Shift left signed ALU register shlsi Shift left signed ALU register by immediate value shr Shift right ALU register shr8 Shift right ALU register by 8 bits shri Shift ...

Page 11: ...ween two different ways of receiving the data Table 13 ch_rxtx internal register in read mode for source sssc to ospc shows the register in read mode when the data from one single microcore is selected This allows transmitting 16 bit data between one microcore and another Table 14 ch_rxtx internal register in read mode for source sumh suml shows the register in read mode when the source sumh or su...

Page 12: ...nt sense block shortcut The current sense block shortcut connects the core to one of the six current sense blocks This shortcut is used primarily for testing the own current current threshold see the ocur field value of the jocf and jocr instructions or waiting for the own current threshold to be reached see the wait instruction s ocur field value Another benefit of shortcuts is the ability to wri...

Page 13: ...current measure operational amplifier gain stoc Set offset compensation 2 15 Output drivers The instructions described in this section are used to control the output drivers Each high side and low side can be turned ON OFF by all microcores if the output access registers are configured properly refer to register 184h to 187h Low side and high side bias needs to be enabled before using the diagnost...

Page 14: ...re the code execution was interrupted If a wait or a conditional jump instruction is interrupted the return address is defined restoring the status of the feedback at the moment the interrupt request occurred 2 16 1 Automatic interrupt Automatic diagnosis interrupt routine address this address defined in the Diag_routine_addr 10Ch and 12Ch section is selected as the new uPC value if an automatic d...

Page 15: ... internal bus e g ALU registers Also the counters can write data into the DRAM or into any of the registers connected to the internal bus this function can be used to perform period measurements on the input signals It is possible to update any terminal count register without stopping the associated counter This feature allows on the fly data correction in the actuated timings All load instruction...

Page 16: ...requested with the wrspi instruction Both the SPI read and write operations are two cycle operations The registers must not be changed while the operation is in progress If the SPI back door is not used the 8 bit register at the address SPI address and the 16 bit register at the address SPI data can be used as spare register Table 23 SPI back door instructions rdspi SPI read request slsa Select SP...

Page 17: ...nary value r4 100 ir 101 mh 110 ml 111 3 1 2 AluGprIrReg subset Table 26 AluGpsIrReg subset description Register label Operand binary value r0 000 r1 001 r2 010 r3 011 r4 100 ir 101 3 1 3 UcReg subset Table 27 UcReg subset description Register label Operand binary value r0 00000 r1 00001 r2 00010 r3 00011 r4 00100 ir 00101 mh 00110 ml 00111 ar 1 01000 aux 01001 jr1 01010 jr2 01011 cnt1 01100 cnt2 ...

Page 18: ... 11010 dac_osoc 11011 dac4h4n 11100 spi_add 11101 irq 4 11110 rxtx 5 11111 1 ar is the ALU arithmetic register arith_reg 2 cr is the control register ctrl_reg 3 sr is the status bits register status_bits 4 irq is the interrupt status register irq_status 5 rxtx is the other channel communication register ch_rxtx 3 1 4 JpReg subset Table 28 JrReg subset description Register label Operand binary valu...

Page 19: ...result is zero RS Addition or subtraction result is negative UU Unsigned underflow UO Unsigned overflow SU Signed underflow SO Signed overflow 0 0 1 1 0 res lmm op1 15 14 13 12 11 10 8 1 0 2 4 5 6 7 9 3 description of operands detailed description of operation symbolic description of operation mnemonic syntax of the instruction and operands simplified instruction description description of intruct...

Page 20: ... register condition jfbkf Jump far on feedback condition jfbkr Jump relative on feedback condition jmpf Unconditional jump far jmpr Unconditional jump relative jocf Jump far on condition jocr Jump relative on condition joidf Jump far on microcore condition joidr Jump relative on microcore condition joslf Jump far on start condition joslr Jump relative on start condition jsrf Jump far on status reg...

Page 21: ...ediate value shl Shift left ALU register shl8 Shift left ALU register of 8 bits shli Shift left the ALU register of immediate value shls Shift left signed ALU register shlsi Shift left signed ALU register of immediate value shr Shift right ALU register shr8 Shift right ALU register of 8 bits shri Shift right the ALU register of immediate value shrs Shift right signed ALU register shrsi Shift right...

Page 22: ...s stslew Set predriver output slew rate mode stmfm Set measurement function MUX stsrb Set status register bit sub Subtract two ALU registers and place the result in one of the ALU registers subi Subtract the value in the immediate register from an ALU register and place the result in an ALU register swap Swap bytes inside ALU register swi Enable disable software interrupt toc2 Convert an integer i...

Page 23: ...Source2 Destination Carry C Assembler syntax add op1 op2 res Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset op2 One of the registers listed in the operand Section 3 1 1 AluReg subset res One of the registers listed in the operand Section 3 1 1 AluReg subset Condition register C Carry over bit RZ Addition or subtraction result is zero RS Addition or subtraction ...

Page 24: ...ster with the immediate value Imm and places the result in the res register Operation Source Immediate value Destination Carry C Assembler syntax addi op1 Imm res Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset op2 One of the registers listed in the operand Section 3 1 1 AluReg subset res One of the registers listed in the operand Section 3 1 1 AluReg subset Tab...

Page 25: ... the value contained in the op1 register The result is placed in the op1 register The initial data stored in the op1 register is lost Operation Source Immediate register Source Assembler syntax and op1 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Ir The ALU immediate register Condition register MN Mask result is 0000h MM Mask result is FFFFh Table 32 and inst...

Page 26: ... description hs1 Select HS1 bias structure hs2 Select HS2 bias structure hs3 Select HS3 bias structure hs4 Select HS4 bias structure hs5 Select HS5 bias structure ls1 Select LS1 bias structure ls2 Select LS2 bias structure ls3 Select LS3 bias structure ls4 Select LS4 bias structure ls5 Select LS5 bias structure ls6 Select LS6 bias structure hs2s Select HS2 strong bias structure hs4s Select HS4 str...

Page 27: ...r VSRC threshold is also impacted by the bootstrap initialization mode Assembler syntax chth SelFbk ThLevel Operands SelFbk Operand defines the threshold comparator to be selected ThLevel This operand specifies one of the 16 threshold level values Operand label Operand description SelFbk operand hs1v HS1 VDS feedback hs1s HS1 VSRC feedback hs2v HS2 VDS feedback hs2s HS2 VSRC feedback hs3v HS3 VDS ...

Page 28: ... Rev 3 0 29 April 2019 28 153 Operand label Operand description lv8 Eighth level 3 5 V lv9 Ninth level 0 10 V lv10 Tenth level 0 20 V lv11 Eleventh level 0 30 V lv12 Twelfth level 0 40 V lv13 Thirteenth level 0 60 V lv14 Fourteenth level 0 70 V lv15 Fifteenth level 0 80 V lv16 Sixteenth level 0 90 V Table 34 chth instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 1 1 SelFbk ThL...

Page 29: ...ide Rev 3 0 29 April 2019 29 153 cp Description Copies the value from the source register op1 into the destination register op2 Assembler syntax cp op1 op2 Operands op1 One of the registers listed in the operand Section 3 1 3 UcReg subset op2 One of the registers listed in the operand Section 3 1 3 UcReg subset Table 35 cp instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 op1 op2 0 0 ...

Page 30: ... same time When the condition Cond is satisfied and the entry is enabled the execution continues either to the address jr1 or jr2 as specified by the op1 parameter Assembler syntax cwef op1 Cond Entry Operands op1 One of the registers listed in the operand Section 3 1 4 JpReg subset Cond Operand defines the condition to be satisfied to enable the jump far Operand label Operand description Cond ope...

Page 31: ... 4 _start Start low start Start high _sc1v Shortcut1 VDS feedback low _sc2v Shortcut2 VDS feedback low _sc3v Shortcut3 VDS feedback low _sc1s Shortcut1 source feedback low _sc2s Shortcut2 source feedback low _sc3s Shortcut3 source feedback low sc1v Shortcut1 VDS feedback high sc2v Shortcut2 VDS feedback high sc3v Shortcut3 VDS feedback high opd Instruction request to ALU executed vb Boost voltage ...

Page 32: ...pril 2019 32 153 Operand label Operand description _cur4h Current feedback 4h low _cur4n Current feedback 4n low ocur Own current feedback high _ocur Own current feedback low Entry operand row1 Wait table row 1 row2 Wait table row 2 row3 Wait table row 3 row4 Wait table row 4 row5 Wait table row 5 row6 Wait table row 6 Table 36 cwef instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 ...

Page 33: ...tination jump address The jump is relative to the instruction Code RAM location The destination address is the actual instruction Code RAM location added to the Dest operand value This 5 bit value is a two s complemented number The MSB is the sign So Dest operand value is in the range of 16 15 Assembler syntax cwer Dest Cond Entry Operands Dest Operand defines the 5 bit relative destination addres...

Page 34: ...igh tc1 Terminal count 1 tc2 Terminal count 2 tc3 Terminal count 3 tc4 Terminal count 4 _start Start low start Start high _sc1v Shortcut1 VDS feedback low _sc2v Shortcut2 VDS feedback low _sc3v Shortcut3 VDS feedback low _sc1s Shortcut1 source feedback low _sc2s Shortcut2 source feedback low _sc3s Shortcut3 source feedback low sc1v Shortcut1 VDS feedback high sc2v Shortcut2 VDS feedback high sc3v ...

Page 35: ...r1 Current feedback 1 low _cur2 Current feedback 2 low _cur3 Current feedback 3 low _cur4l Current feedback 56l low _cur4h Current feedback 56h low _cur4n Current feedback 4n low ocur Own current feedback high _ocur Own current feedback low Entry operand row1 Wait table row 1 row2 Wait table row 2 row3 Wait table row 3 row4 Wait table row 4 row5 Wait table row 5 row6 Wait table row 6 Table 37 inst...

Page 36: ...nt measurement block At reset the default shortcut setting is the following Shortcut Uc0Ch1 Uc1Ch1 Uc0Ch2 Uc1Ch2 ShrtCur dac1 dac2 dac3 dac4 Assembler syntax dfcsct ShrtCur Operands ShrtCur Operand defines which current measurement block is dedicated to the shortcut Operand label Operand description Operand binary value dac1 DAC1 is selected as current shortcut 00 dac2 DAC2 is selected as current ...

Page 37: ...e the async or sync mode the low side use for DCDC has to be set as shortcut 2 ex dfsct undef ls7 undef At reset the default shortcut setting is undefined Assembler syntax dfsct Shrt1 Shrt2 Shrt3 Operands Shrt1 Shrt2 and Shrt3 Operands define to which predriver the shortcut is dedicated Operand label Operand description hs1 High side predriver 1 hs2 High side predriver 2 hs3 High side predriver 3 ...

Page 38: ...es the monitored predriver and VDS or VSRC feedback Operand label Operand description hs1v High side predriver 1 VDS feedback hs1s High side predriver 1 SRC feedback hs2v High side predriver 2 VDS feedback hs2s High side predriver 2 SRC feedback hs3v High side predriver 3 VDS feedback hs3s High side predriver 3 SRC feedback hs4v High side predriver 4 VDS feedback hs4s High side predriver 4 SRC fee...

Page 39: ...errupt procedure for error handling is triggered The operation is successful only if the microcore has the right to drive the related outputs The drive right is granted by setting the related bits in the Out_acc_ucX_chY 184h 185h 186h 187h configuration registers At reset the automatic diagnosis is disabled Assembler syntax endiaga Diag Operands Diag Operand defines the diagnosis status Operand la...

Page 40: ...on is successful only if the microcore has the right to drive the related outputs The drive right is granted by setting the related bits in the Out_acc_ucX_chY 184h 185h 186h 187h configuration registers At reset the automatic diagnosis are disabled Assembler syntax endiags Diag_sh1_vds Diag_sh1_src Diag_sh2_vds Diag_sh3_vds Operands Diag _sh1_vds Diag_sh2_vds and Diag_sh3_vds Operands correspondi...

Page 41: ...drivers interrupt Reading or writing the Driver_status register 1D2h in case of automatic diagnosis interrupt This register must be configured such as to be reset at read The reset value is none Assembler syntax iconf Conf Operands Conf Operand defines interrupt behaviors Operand label Operand description none The microcore ignores all automatic interrupt return request continue When an interrupt ...

Page 42: ...rogram counter uPC is handled returning from the interrupt routine Operand label Operand description continue The execution is resumed at the address stored in the 10 LSBs of the interrupt register restart The execution is resumed at the address stored in the uc0_entry_point 10Ah and 12Ah or uc1_entry_point 10Bh and 12Bh Rst Operand defines if the pending interrupt queue is clear when the iret ins...

Page 43: ...condition that triggers the jump The arithmetic conditions are stored into the ALU condition register Operand label Operand description Operand binary value opd OD Operation complete 0000 ovs SO Overflow with signed operands 0001 uns SU Underflow with signed operands 0010 ovu UO Overflow with unsigned operands 0011 unu UU Underflow with unsigned operands 0100 sgn CS Sign of result 0101 zero RZ Res...

Page 44: ...tion address in the range of 16 15 BitSel Operand defines the arithmetic condition that triggers the jump The arithmetic conditions are stored into the ALU condition register Operand label Operand description Operand binary value opd OD Operation complete 0000 ovs SO Overflow with signed operands 0001 uns SU Underflow with signed operands 0010 ovu UO Overflow with unsigned operands 0011 unu UU Und...

Page 45: ...ors PT2001SWUG PT2001 programming guide and instruction set PT2001SWUG All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 45 153 ...

Page 46: ...tion 3 1 4 JpReg subset CrSel Operand defines the control register condition Ctrl_reg_uc0 101h and 121h and Ctrl_reg_uc1 102h and 122h registers that triggers the jump Operand label Operand description Operand binary value b0 Control register bit 0 LSB 0000 b1 Control register bit 1 0001 b2 Control register bit 2 0010 b3 Control register bit 3 0011 b4 Control register bit 4 0100 b5 Control registe...

Page 47: ...on set PT2001SWUG All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 47 153 Table 47 jcrf instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 Pol CrSel op1 0 1 0 0 ...

Page 48: ...Sel Pol Operands Dest Operand defines the 5 bit relative destination address in the range of 16 15 CrSel Operand defines the control register condition Ctrl_reg_uc0 101h 121h and Ctrl_reg_uc1 102h 122h registers that triggers the jump Operand label Operand description Operand binary value b0 Control register bit 0 LSB 0000 b1 Control register bit 1 0001 b2 Control register bit 2 0010 b3 Control re...

Page 49: ...uction set PT2001SWUG All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 49 153 Table 48 jcrr instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 Pol CrSel Dest ...

Page 50: ...ue hs1v High side predriver 1 VDS feedback 000000 hs1s High side predriver 1 VSRC feedback 000001 hs2v High side predriver 2 VDS feedback 000010 hs2s High side predriver 2 VSRC feedback 000011 hs3v High side predriver 3 VDS feedback 000100 hs3s High side predriver 3 VSRC feedback 000101 hs4v High side predriver 4 VDS feedback 000110 hs4s High side predriver 4 VSRC feedback 000111 hs5v High side pr...

Page 51: ...nation address in the range of 16 15 SelFbk Operand defines the feedback signal condition Operand label Operand description Operand binary value hs1v High side predriver 1 VDS feedback 0000 hs1s High side predriver 1 VSRC feedback 0001 hs2v High side predriver 2 VDS feedback 0010 hs2s High side predriver 2 VSRC feedback 0011 hs3v High side predriver 3 VDS feedback 0100 hs3s High side predriver 3 V...

Page 52: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 1 SelFbk Pol Dest jmpf Description Configures the unconditional jump The destination address defined in one of the jump registers defined by the operand op1 The destination address is any of the absolute Code RAM location Assembler syntax jmpf op1 Operands op1 One of the registers listed in the operand Section 3 1 4 JpReg subset Table 51 jmpf instruction fo...

Page 53: ...location The jump is relative to the instruction Code RAM location The destination address is the actual instruction Code RAM location added to the Dest operand value This 5 bit value is a two s complemented number The MSB is the sign So Dest operand value is in the range of 16 15 Assembler syntax jmpr Dest Operands Dest Operand defines the 5 bit relative destination address in the range of 16 15 ...

Page 54: ...config 112h and 132h The feedback from current measurement 4 can only be checked if this channel is activated via the flags_source 1A3h register If the channel is activated flag 12 can not be checked anymore The destination address defined by the op1 register is any of the absolute Code RAM location Assembler syntax jocf op1 Cond Operands op1 One of the registers listed in the operand Section 3 1 ...

Page 55: ...t 2 tc3 Terminal count 3 tc4 Terminal count 4 _start Start low start Start high _sc1v Shortcut1 VDS feedback low _sc2v Shortcut2 VDS feedback low _sc3v Shortcut3 VDS feedback low _sc1s Shortcut1 source feedback low _sc2s Shortcut2 source feedback low _sc3s Shortcut3 source feedback low sc1v Shortcut1 VDS feedback high sc2v Shortcut2 VDS feedback high sc3v Shortcut3 VDS feedback high opd Instructio...

Page 56: ... rights reserved User guide Rev 3 0 29 April 2019 56 153 Operand label Operand description _cur3 Current feedback 3 low _cur4l Current feedback 5 6l low _cur4h Current feedback 5 6h low _cur4n Current feedback 5 6n low ocur Own current feedback high _ocur Own current feedback low Table 53 jocf instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 Cond op1 0 0 0 0 ...

Page 57: ...ed to the Dest operand value This 5 bit value is a two s complemented number The MSB is the sign So Dest operand value is in the range of 16 15 It is possible to supply a label for this field Assembler syntax jocr Dest Cond Operands Dest Operand defines the 5 bit relative destination address in the range of 16 15 Cond Operand defines the condition to be satisfied to enable the relative jump Operan...

Page 58: ...rtcut1 VDS feedback low _sc2v Shortcut2 VDS feedback low _sc3v Shortcut3 VDS feedback low _sc1s Shortcut1 source feedback low _sc2s Shortcut2 source feedback low _sc3s Shortcut3 source feedback low sc1v Shortcut1 VDS feedback high sc2v Shortcut2 VDS feedback high sc3v Shortcut3 VDS feedback high opd Instruction request to ALU executed vb Boost voltage high _vb Boost voltage low cur1 Current feedba...

Page 59: ...nt is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 59 153 Operand label Operand description _cur4n Current feedback 5 6n low ocur Own current feedback high _ocur Own current feedback low Table 54 jocr instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 Cond Dest ...

Page 60: ...ed such as the next executed instruction is located into the destination address contained in one of the jump registers The destination address defined by the op1 register is any of the absolute Code RAM location Assembler syntax joidf op1 UcSel Operands op1 One of the registers listed in the operand Section 3 1 4 JpReg subset UcSel Operand defines the microcore identifier condition Operand label ...

Page 61: ...jump is relative to the instruction Code RAM location The destination address is the actual instruction Code RAM location added to the Dest operand value This 5 bit value is a two s complemented number The MSB is the sign So Dest operand value is in the range of 16 15 Assembler syntax joidr Dest UcSel Operands Dest Operand defines the 5 bit relative destination address in the range of 16 15 UcSel ...

Page 62: ...op1 One of the registers listed in the operand Section 3 1 4 JpReg subset StSel Operand defines the start condition to be satisfied to enable the jump far Operand label Operand description none No start latched start1 Start 1 latched start2 Start 2 latched start12 Start 1 2 latched start3 Start 3 latched start13 Start 1 3 latched start23 Start 2 3 latched start123 Start 1 2 3 latched start4 Start ...

Page 63: ...t36 start 3 6 latched start136 start 1 3 6 latched start236 start 2 3 6 latched start1236 start 1 2 3 6 latched start46 start 4 6 latched start146 start 1 4 6 latched start246 start 2 4 6 latched start1246 start 1 2 4 6 latched start346 start 3 4 6 latched start1346 start 1 3 4 6 latched start2346 start 2 3 4 6 latched start12346 start 1 2 3 4 6 latched start56 start 5 6 latched start156 start 1 5...

Page 64: ...document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 64 153 Operand label Operand description start23456 start 2 3 4 5 6 latched start123456 start 1 2 3 4 5 6 latched Table 57 joslf instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 StSel op1 0 0 0 1 ...

Page 65: ...d value is in the range of 16 15 Assembler syntax joslr Dest StSel Operands Dest Operand defines the 5 bit relative destination address in the range of 16 15 StSel Operand defines the start condition to be satisfied to enable the jump far Operand label Operand description none No start latched start1 Start 1 latched start2 Start 2 latched start12 Start 1 2 latched start3 Start 3 latched start13 St...

Page 66: ...art126 start 1 2 6 latched start36 start 3 6 latched start136 start 1 3 6 latched start236 start 2 3 6 latched start1236 start 1 2 3 6 latched start46 start 4 6 latched start146 start 1 4 6 latched start246 start 2 4 6 latched start1246 start 1 2 4 6 latched start346 start 3 4 6 latched start1346 start 1 3 4 6 latched start2346 start 2 3 4 6 latched start12346 start 1 2 3 4 6 latched start56 start...

Page 67: ...bject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 67 153 Operand label Operand description start13456 start 1 3 4 5 6 latched start23456 start 2 3 4 5 6 latched start123456 start 1 2 3 4 5 6 latched Table 58 joslr instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 StSel Dest ...

Page 68: ...jsrf op1 SrSel Pol Operands op1 One of the registers listed in the operand Section 3 1 4 JpReg subset SrSel Operand defines the status register condition Status_reg_uc0 105h 125h and Status_reg_uc1 106h 126h that triggers the jump Operand label Operand description b0 Status register bit 0 LSB b1 Status register bit 1 b2 Status register bit 2 b3 Status register bit 3 b4 Status register bit 4 b5 Sta...

Page 69: ...on set PT2001SWUG All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 69 153 Table 59 jsrf instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 Pol SrSel op1 0 1 0 1 ...

Page 70: ...Dest operand value is in the range of 16 15 Assembler syntax jsrr Dest SrSel Pol Operands Dest Operand defines the 5 bit relative destination address in the range of 16 15 SrSel Operand defines the status register condition Status_reg_uc0 105h 125h and Status_reg_uc1 106h 126h registers that triggers the jump Operand label Operand description b0 Status register bit 0 LSB b1 Status register bit 1 b...

Page 71: ...uction set PT2001SWUG All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 71 153 Table 60 jsrr instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 Pol SSel Dest ...

Page 72: ... executed instruction is located into the destination address contained in one of the jump registers When jump to subroutine is called the current program counter value uPC is stored in the auxiliary register aux to handle the end of subroutine return The destination address defined by the op1 register is any of the absolute Code RAM location Assembler syntax jtsf op1 Operands op1 One of the regis...

Page 73: ...er value uPC is stored into the auxiliary register aux to handle end of subroutine return The jump is relative to the instruction Code RAM location The destination address is the actual instruction Code RAM location added to the Dest operand value This 5 bit value is a two s complemented number The MSB is the sign So Dest operand value is in the range of 16 15 Assembler syntax jtsr Dest Operands D...

Page 74: ...rst The counter value is maintained only the end of counter is modified rst The counter value is reset to zero and starts to count from zero Sh1 Sh2 Operands set the first and second shortcuts related to the corresponding outputs The output shortcuts are defined using the dfsct instruction Operand label Operand description keep No changes maintains the previous setting off Shortcut 1 or 2 turns OF...

Page 75: ...ler syntax ldcd Rst Ofs Sh1 Sh2 Dram Eoc Operands Rst Operand Boolean defines if the selected counter value must be reset to zero or must be unchanged Operand label Operand description _rst The counter value is maintained only the end of count is modified rst The counter value is reset to zero and start to count from zero Ofs Operands set Data RAM addressing mode Operand label Operand description ...

Page 76: ...ction set PT2001SWUG All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 76 153 Table 64 ldcd instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 Ofs Rst Sh1 Sh2 Eoc Dram ...

Page 77: ...esult in one of the ALU registers Loads the Value8 data in the 8 MSB of the immediate register ir Assembler syntax ldirh Value8 RstL Value8 Operand defines the 8 bit value to be loaded into the 8 MSB of the immediate register RstL Operand Boolean defines if set to zero the low byte 7 0 of ir register Operand label Operand description _rst No change on the ir 7 0 rst Set the Zero the ir 7 0 Table 6...

Page 78: ... one of the ALU registers Loads the Value8 data in the 8 LSB of the immediate register ir Assembler syntax ldirl Value8 RstH Operands Value8 Operand defines the 8 bit value to be loaded into the 8 MSB of the immediate register RstH Operand Boolean defines if set to zero the high byte 15 8 of ir register Operand label Operand description _rst No change on the ir 15 8 rst Set the Zero on the ir 15 8...

Page 79: ... ldjr1 Description Loads the Value10 data in the 16 bit jump register 1 jr1 The operand Value10 can be replaced by a label The compiler automatically substitutes the label if used with the defined value Assembler syntax ldjr1 Value10 Operands Value10 Operand defines the 10 bit value to be loading into the jump register 1 Table 67 ldjr1 instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0...

Page 80: ...019 80 153 ldjr2 Description Loads the Value10 data in the 16 bit jump register 2 jr2 The operand Value10 can be replaced by a label The compiler automatically substitutes the label if used with the defined value Assembler syntax ldjr2 Value10 Operands Value10 Operand defines the 10 bit value to be loading into the jump register 2 Table 68 ldjr2 instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 81: ...itable Data RAM address The Data RAM address is accessed according to the Boolean operand Ofs using the Immediate addressing mode IM Indexed addressing mode XM In that case address base is added the address Dram The address base is set using the stab instructions Assembler syntax load Dram op1 Ofs Operands Dram Operand defines the 6 bit Data RAM address op1 One of the registers listed in the opera...

Page 82: ...atenation of the multiplication result registers mh and ml mh contains the 16 MSB ml contains the 16 MSB The multiplication requires 32 ck clock cycles to be completed Operation Source1 x Source2 Destination Assembler syntax mul op1 op2 Operands op1 One of the registers listed in the operand Section 3 1 2 AluGprIrReg subset op2 One of the registers listed in the operand Section 3 1 2 AluGprIrReg s...

Page 83: ...2 register The reg32 register is the concatenation of the multiplication result registers mh and ml mh contains the 16 MSB ml contains the 16 LSB The multiplication requires 32 ck clock cycles to be completed Assembler syntax muli op1 Imm Operands op1 One of the registers listed in the operand AluGprIrReg subset Imm The Imm 4 bit immediate data register Condition register MO Multiplication shift o...

Page 84: ...9 April 2019 84 153 not Description Inverts each bit of the op1 register and places the result in the op1 register Operation Source Source Assembler syntax not op1 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Condition register MN Mask result is 0000h MM Mask result is FFFFh Table 72 not instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 1 0...

Page 85: ...ription Applies the OR mask stored in the Immediate Register ir to the op1 register and places the result in the op1 register Operation Source Immediate register Source Assembler syntax or op1 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Condition register MN Mask result is 0000h MM Mask result is FFFFh Table 73 or instruction format 15 14 13 12 11 10 9 8 7 6...

Page 86: ... Description Requests an SPI backdoor read The address must previously be defined in the SPI address register spi_add The rdspi instruction requires 2 ck cycle to complete operation The SPI address register must not be changed on the following instruction otherwise the operation fails and the read data is dummy Assembler syntax rdspi Table 74 rdspi instruction format 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 87: ...he interrupt return register corresponding to the 10 LSB of the uc0_irq_status register 10Fh 12Fh and for uc1_irq_status 110h 130h By default the return address of an interrupt is the line where the code was interrupted In the case of a software interrupt the return address is the address where the code was interrupted 1 A software interrupt must not be interrupted Assembler syntax reqi id Operand...

Page 88: ...ser guide Rev 3 0 29 April 2019 88 153 rfs Description Ends a subroutine To continue the code execution the program counter uPC is loaded with the content of the auxiliary register aux automatically updated when the subroutine was called with the instructions jtsf and jtsr Assembler syntax rfs Table 76 rfs instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 0 ...

Page 89: ...sters to be reset Operand label Operand description sr Reset status bits of the status registers cr Reset control register sr_diag_halt Reset status bits automatic diagnosis register and re enables the possibility to generate automatic diagnosis interrupts all Reset status bits control register automatic diagnosis register and re enables the possibility to generate automatic diagnosis interrupts d...

Page 90: ...9 April 2019 90 153 rstsl Description Resets the Start_latch_ucx register This instruction is active only if the Smart Latch mode is enabled The smart mode register can be activated by setting the bits smart_start_uc0 and smart_start_uc1 of the Start_config_reg_Part2 registers 104h 124h Assembler syntax rstsl Table 78 rstsl instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1...

Page 91: ...he reg32 register is the concatenation of the multiplication result registers mh and ml mh contains the 16 MSB ml contains the 16 LSB To be completed the shift operation requires a number of ck clock cycles corresponding to the op1 register value Operation Source1 factor Source Assembler syntax sh32l op1 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Condition ...

Page 92: ...lue factor The reg32 register is the concatenation of the multiplication result registers mh and ml mh contains the 16 MSB ml contains the 16 LSB To be completed the shift operation requires a number of ck clock cycles corresponding to the immediate value Operation Source1 Immediate value Source Assembler syntax sh32li Imm Operands Imm The Imm 4 bit immediate data register Condition register SB Sh...

Page 93: ...he reg32 register is the concatenation of the multiplication result registers mh and ml mh contains the 16 MSB ml contains the 16 LSB To be completed the shift operation requires a number of ck clock cycles corresponding to the op1 register value Operation Source1 factor Source Assembler syntax sh32r op1 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Condition ...

Page 94: ...e value The reg32 register is the concatenation of the multiplication result registers mh and ml mh contains the 16 MSB ml contains the 16 LSB To be completed the shift operation requires a number of ck clock cycles corresponding to the immediate value Operation Source1 Immediate value Source Assembler syntax sh32ri Imm Operands Imm The Imm 4 bit immediate data register Condition register SB Shift...

Page 95: ...e op2 register value factor To be completed the shift operation requires a number of ck clock cycles corresponding to the op2 register value Operation Source1 factor Source Assembler syntax shl op1 op2 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset op2 One of the registers listed in the operand Section 3 1 1 AluReg subset Condition register SB Shift out bit MO ...

Page 96: ...53 shl8 Description Shifts the op1 register 8 positions left To be completed the shift operation requires one ck clock cycles Operation Source1 8 Source Assembler syntax shl8 op1 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Condition register SB Shift out bit MO Multiplication shift overflow Table 84 shl8 instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 97: ...according to the immediate value Imm To be completed the shift operation requires a number of ck clock cycles corresponding to the immediate value Imm Operation Source1 Immediate value Source Assembler syntax shl op1 Imm Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Imm The Imm 4 bit immediate data register Condition register SB Shift out bit MO Multiplication...

Page 98: ... a two s complement number The MBS sign bit is unchanged during the shift operation To be completed the shift operation requires a number of ck clock cycles corresponding to the op2 register value Operation Source1 factor Source Assembler syntax shls op1 op2 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset op2 One of the registers listed in the operand Section 3 ...

Page 99: ...handled as a two s complement number The MBS sign bit is unchanged during the shift operation To be completed the shift operation requires a number of ck clock cycles corresponding to the immediate value Imm Operation Source1 Immediate value Source Assembler syntax shls op1 Imm Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Imm The Imm 4 bit immediate data regi...

Page 100: ...r value factor To be completed the shift operation requires a number of ck clock cycles corresponding to the op2 register value Operation Source1 factor Source Assembler syntax shr op1 op2 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset op2 One of the registers listed in the operand Section 3 1 1 AluReg subset Condition register SB Shift out bit ML Multiplicatio...

Page 101: ... shr8 Description Shift the op1 register 8 positions right To be completed the shift operation requires one ck clock cycle Operation Source1 8 Source Assembler syntax shr8 op1 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Condition register SB Shift out bit ML Multiplication shift precision loss Table 89 shr8 instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

Page 102: ...cording to the immediate value Imm To be completed the shift operation requires a number of ck clock cycles corresponding to the immediate value Imm Operation Source1 Immediate value Source Assembler syntax shri op1 Imm Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Imm The Imm 4 bit immediate data register Condition register SB Shift out bit ML Multiplication ...

Page 103: ... two s complement number The MBS sign bit is unchanged during the shift operation To be completed the shift operation requires a number of ck clock cycles corresponding to the op2 register value Operation Source1 factor Source Assembler syntax shrs op1 op2 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset op2 One of the registers listed in the operand Section 3 1 ...

Page 104: ... handled as a two s complement number The MBS sign bit is unchanged during the shift operation To be completed the shift operation requires a number of ck clock cycles corresponding to the immediate value Imm Operation Source Immediate value Source Assembler syntax shrsi op1 Imm Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Imm The Imm 4 bit immediate data reg...

Page 105: ...ta RAM Indexed Addressing Mode XM The reset value of SelBase is reg Assembler syntax slab SelBase Operands SelBase Operand defines the register to be used to determine the data RAM address base Operand label Operand description reg Use the dedicated address base add_base register In this case the address base is defined with the stab instruction ir Use the ALU ir register as address base Table 93 ...

Page 106: ... 184h 185h 186h 187h configuration registers The reset of Ref value is boost Assembler syntax slfbk Ref Diag Operands Ref Operand defines the feedback reference for both VDS of the high side predrivers 2 and 4 Operand label Operand description boost Both VDS of the high side predrivers 2 and 4 are referred to boost voltage VBOOST pin bat Both VDS of the high side predrivers 2 and 4 are referred to...

Page 107: ...st Assembler syntax slfbk Dest Ref Diag Operands Dest Shortcut used for VDS feedback Operand label Operand description Sh1 Shortcut 1 Sh2 Shortcut 2 Sh3 Shortcut 3 Ref Operand defines the feedback reference for both VDSs of the high side predrivers 2 4 and 6 Operand label Operand description boost Both VDSs of the high side predrivers 2 and 4 are referred to boost voltage VBOOST pin bat Both VDSs ...

Page 108: ...ng the address used on SPI read and write instructions rdspi and wrspi The reset values of SelSpi is reg Assembler syntax slsa SelSpi Operands SelSpi Operand defines the register containing the SPI address Operand label Operand description Operand binary value reg Use the dedicated address register spi_ add 0 ir Use the ALU ir register as SPI address 1 Table 96 slsa instruction format 15 14 13 12 ...

Page 109: ...base The address base register is a 6 bit register containing the address base used in the Data RAM Indexed Addressing Mode XM The operand add_base can be identified with a univocal label The compiler automatically substitutes the define label if used with the suitable address Assembler syntax stab Add_Base Operands add_base Operand defines the 6 bit register containing the Address Base Table 97 s...

Page 110: ...reset value of AdcMode is off Assembler syntax stadc AdcMode DacTarget Operands AdcMode Operand activates the ADC mode on the selected current measurement block Operand label Operand description off The current measurement block compares the current flowing in the actuator with a threshold nominal behavior on The current measurement block performs an analog to digital conversion of the current flo...

Page 111: ...rs PT2001SWUG PT2001 programming guide and instruction set PT2001SWUG All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 111 153 ...

Page 112: ...f the resulting value exceeds the result register capacity it leads to overflow detection but no saturation The ALU instruction operands are handled as a C complement number signed number If the resulting value exceeds the result register capacity it leads to overflow detection and saturation The ALU instruction operands are handled as a positive number unsigned number If the resulting value excee...

Page 113: ...rs PT2001SWUG PT2001 programming guide and instruction set PT2001SWUG All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 113 153 ...

Page 114: ...er syntax stcrb Logic CrbSel Operands Logic Operand defines the logic level value Operand label Operand description low Low level high High level CrbSel Operand defines the control register bit to be selected Operand label Operand description b8 Control register bit 8 b9 Control register bit 9 b10 Control register bit 10 b11 Control register bit 11 b12 Control register bit 12 b13 Control register ...

Page 115: ...he microcore s shared register accessed by the microcore executing the stcrt instruction The UcId reset value is sssc Assembler syntax stcrt UcId Operands UcId Operand defines the microcore shared register to be access Operand label Operand description sssc The microcore executing the code ossc The other microcore in the same channel ssoc The same microcore in the other channel osoc The other micr...

Page 116: ...the microcore sync or perform the automatic current regulation async between threshold 4l and 4h The ModeDC reset value is sync Assembler syntax stdcctl ModeDC Operands ModeDC Operand defines the DC DC control mode Operand label Operand description sync DCDC is controlled by the microcore async DCDC performs an automatic current control between threshold 4l and 4h Table 102 stdcctl instruction for...

Page 117: ...t address is accessed The result is available in the 8 lower bits offset_access_mode dac4neg_access_mode the offset register for the dac address or the dac4neg value for the dac4h4n_boost address is accessed The result is available in the 13 8 bits if reading an offset in the 11 8 bits if reading dac4neg full_access_mode dac4h4n_access_mode both the dac value and the offset register for the dac ad...

Page 118: ...e_mode only the 8 MSBs of the source Data RAM are accessed The result is available in the 8 lower bits of the destination register The upper 8 bits of the destination register is set to 00h dram_swapbyte_mode the 8 LSBs and 8 MSBs of the source dram are accessed swapped and is available at the destination register This read mode is valid after the load and ldcd instructions following this stdrm in...

Page 119: ...sk default value is nomask The Switch default value is bsneutral Assembler syntax steoa Mask Switch Operands Mask Operand sets the VDS threshold mask Operand label Operand description nomask VSRC threshold monitoring of the selected HS is unchanged mask VSRC threshold monitoring of the selected HS is masked to zero Switch Operand sets the end of actuation mode Operand label Operand description kee...

Page 120: ...sembler syntax stf Logic FlgSel Operands Logic Operand defines the logic level value Operand label Operand description low Low level high High level FlgSel Operand defines the flag bit to be selected Operand label Operand description b0 Flag bit 0 b1 Flag bit 1 b2 Flag bit 2 b3 Flag bit 3 b4 Flag bit 4 b5 Flag bit 5 b6 Flag bit 6 b7 Flag bit 7 b8 Flag bit 8 b9 Flag bit 9 b10 Flag bit 10 b11 Flag b...

Page 121: ...ing predriver if Shortcut1 is HS2 then LS6 is set as freewheeling predriver if Shortcut1 is HS3 then LS7 is set as freewheeling predriver if Shortcut1 is HS4 then HS5 is set as freewheeling predriver if Shortcut1 is HS5 then LS4 is set as freewheeling predriver The shortcuts are set using the dfsct instruction This operation is successful only if the microcore has the right to drive the output it ...

Page 122: ... 132h The Gain reset value is gain 5 8 Assembler syntax stgn Gain OpAmp Operands Gain Operand defines the current measure operational amplifier gain Operand label Operand description Operand binary value gain5 8 Operational amplifier gain set to 5 8 00 gain8 7 Operational amplifier gain set to 8 7 01 gain12 6 Operational amplifier gain set to 12 5 10 gain19 3 Operational amplifier gain set to 19 3...

Page 123: ...reserved User guide Rev 3 0 29 April 2019 123 153 stirq Description Set the IRQB output pin The Logic reset value is high Assembler syntax stirq Logic Operands Logic Operand defines the logic level of the IRQB pin Operand label Operand description low Low level high High level Table 109 stirq instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 Logic ...

Page 124: ...nfiguration registers Assembler syntax sto OutSel Out Operands OutSel Operand defines the handled output Operand label Operand description hs1 High side predriver 1 hs2 High side predriver 2 hs3 High side predriver 3 hs4 High side predriver 4 hs5 High side predriver 5 ls1 Low side predriver 1 ls2 Low side predriver 2 ls3 Low side predriver 3 ls4 Low side predriver 4 ls5 Low side predriver 5 ls6 Lo...

Page 125: ...gister 188h and Cur_block_access_2 Register 189h The other channel is selected by SPI register bit refer to Dac_rxtx_cr_config 112h 132h The Ctrl reset value is off for all current measurement blocks Assembler syntax stoc Ctrl DacTraget Operands Ctrl Operands sets offset compensation state Operand label Operand description off Disable the offset compensation on Enable the offset compensation DacTa...

Page 126: ...Data RAM address The Data RAM address is accessed according to the Boolean operand Ofs using the Immediate addressing mode IM Indexed addressing mode XM In that case the address base is added to the address Dram The address base is set using the stab instructions Assembler syntax store op1 Dram Ofs Operands op1 One of the registers listed in the operand Section 3 1 3 UcReg subset Dram Operand defi...

Page 127: ... operation is successful only if the microcore has the right to drive the related outputs The drive right is granted by setting the related bits in the Out_acc_ucX_chY 184h 185h 186h 187h configuration registers Assembler syntax stos Out1 Out2 Out3 Operands Out1 Out2 and Out3 Operands sets output state Operand label Operand description keep No changes maintains the previous setting off Output disa...

Page 128: ..._chY 184h 185h 186h 187h configuration registers The SlMode reset value is normal When switching the slew rate from slow to fast the new slew rate is valid after typically one ck cycle 166 ns considering fCK 6 0 MHz When switching from fast to slow it takes typically four ck cycles 666 ns considering fCK 6 0 MHz until the new slew rate is effective Assembler syntax stslew SlMode Operands SlMode Op...

Page 129: ...ls s_hs oax Switch Operands d_ls Operand select the D_LSx multiplexer input s_hs Operand select the S_HSx multiplexer input oax Operand select the OAx used for the measurement function Switch Operand enable disable the OAx oa_enable Table 115 d_ls Operand label Operand description Operand binary value sh2 D_LS of shortcut 2 selected 00 sh3 D_LS of shortcut 3 selected 01 agnd AGND selected 10 keep ...

Page 130: ... document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 130 153 Table 118 Switch Operand label Operand description Operand binary value en oax enabled 0 dis oax disabled 1 Instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 Switch oax s_hs d_ls 1 0 0 0 ...

Page 131: ...level value Operand label Operand description low Low level high High level SrbSel Operand defines the status register bit to be selected Operand label Operand description b0 Status register bit 0 LSB b1 Status register bit 1 b2 Status register bit 2 b3 Status register bit 3 b4 Status register bit 4 b5 Status register bit 5 b6 Status register bit 6 b7 Status register bit 7 b8 Status register bit 8...

Page 132: ...ration Source1 Source2 Destination Assembler syntax sub op1 op2 res Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset op2 One of the registers listed in the operand Section 3 1 1 AluReg subset res One of the registers listed in the operand Section 3 1 1 AluReg subset Condition register RZ Addition or subtraction result is zero RS Addition or subtraction result is ...

Page 133: ...es register Operation Source1 Immediate value Destination Assembler syntax subi op1 Imm res Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Imm The Imm 4 bit immediate data register res One of the registers listed in the operand Section 3 1 1 AluReg subset Condition register RZ Addition or subtraction result is zero RS Addition or subtraction result is negative ...

Page 134: ...l rights reserved User guide Rev 3 0 29 April 2019 134 153 swap Description Swaps the high byte and the low byte of the register op1 Operation Source 0 7 Source 8 15 Assembler syntax swap op1 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset Table 122 swap instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 1 1 0 0 op1 ...

Page 135: ...all software interrupts and from start edges for a microcore HW interrupts from automatic diagnosis driver disable or loss of clock are not disabled The Switch reset value is on all SW interrupts enabled Assembler syntax swi Switch Operands Switch Operands enable or disable SW interrupts Operand label Operand description on SW interrupts on off SW interrupts off Table 123 swi instruction format 15...

Page 136: ...register into a two s complement format If the conversion bit in the arithmetic condition register is zero the toc2 instruction makes the most significant bit in the operand register zero If the conversion bit is one then it returns the two s complement of the operand bits 14 0 only register Assembler syntax toc2 op1 Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subs...

Page 137: ...sion bit CS of the arithmetic condition register arith_reg The MSB of the operand is either XORed with the existing conversion bit CS of the ALU condition register if the instruction is called with the _rst parameter or replaces it if the instruction is called with the rst parameter Assembler syntax toint op1 Rst Operands op1 One of the registers listed in the operand Section 3 1 1 AluReg subset R...

Page 138: ...ble row enabled infinite loop 000000 row1 Wait table row 1 enabled 000001 row2 Wait table row 2 enabled 000010 row12 Wait table row 1 2 enabled 000011 row3 Wait table row 3 enabled 000100 row13 Wait table row 1 3 enabled 000101 row23 Wait table row 2 3 enabled 000110 row123 Wait table row 1 2 3 enabled 000111 row4 Wait table row 4 enabled 001000 row14 Wait table row 1 4 enabled 001001 row24 Wait t...

Page 139: ...36 Wait table row 1 3 6 enabled 100111 row146 Wait table row 1 4 6 enabled 101000 row156 Wait table row 1 5 6 enabled 101001 row236 Wait table row 2 3 6 enabled 101010 row246 Wait table row 2 4 6 enabled 101011 row256 Wait table row 2 5 6 enabled 101100 row346 Wait table row 3 4 6 enabled 101101 row456 Wait table row 4 5 6 enabled 101110 row1236 Wait table row 1 2 3 6 enabled 101111 row1246 Wait t...

Page 140: ...is document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 140 153 Table 126 wait instruction format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 0 0 0 WaitMask row 6 disabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 0 0 1 1 WaitMask row 6 enabled ...

Page 141: ...ss must previously be defined in the SPI address register spi_add The data must previously be defined in the SPI data register spi_data The wrspi instruction requires 2 ck cycles to complete The SPI address register and SPI data register must not be changed on the following instruction otherwise the operation fails and the written data is dummy Assembler syntax wrspi Table 127 wrspi instruction fo...

Page 142: ...gineer in a source file coding the PT2001 specific instructions in assembler language The extension dfi or psc is generally used for the source file Any other extension can be used as a source code extension with the exception of assembler s input file extensions link xml key or output file extensions cip hex bin asm log reg cip bin cip hex The assembler language coding rules are defined in the fo...

Page 143: ...nt value definition that is used locally in the source code The constant definitions must terminate in the character The define syntax is as follows define SymbolName SymbolValue The constant definitions are placed At the beginning of the line Or after the final comment field character The constant definition must be placed in an instruction line No other item such as an instruction label or inclu...

Page 144: ... label refers to a line code where the label is set For example if the label Init is located on line 7 any instruction using this label refers to line 7 Labels must be placed at the beginning of the line or after the final character of a comment field These labels end with the symbol All labels must be followed by an instruction They must be unique must not already have been used as a SymbolName i...

Page 145: ...019 145 153 The conditional assembly considers a branch only if its parameter is defined whatever its value may be Using an ELSE branch is optional All the instructions placed before the IF label and after the ENDIF label are excluded from the conditional code block and are assembled Only one level of condition assembly is supported so an IF function cannot be nested within another IF function Con...

Page 146: ...tion provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 146 153 5 Example source code This code can be used with the FRDMPT2001EVM 5 1 Channel 1 Ucore0 controls injectors 1 and 2 5 2 Channel 1 Ucore1 controls injectors 3 and 4 ...

Page 147: ...rs PT2001SWUG PT2001 programming guide and instruction set PT2001SWUG All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 147 153 ...

Page 148: ...001 programming guide and instruction set PT2001SWUG All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User guide Rev 3 0 29 April 2019 148 153 5 3 Channel 2 Ucore0 DCDC control ...

Page 149: ...hannel 2 Ucore1 Fuel Pump Drive Source Code 6 Revision history Revision history Rev Date Description v 3 20190429 Table 29 added stmfm instruction Section 3 2 2 added description for stmfm instruction v 2 20190415 Section 2 3 replaced 8 startx pins by 6 startx pins Section 3 2 2 ldca updated the description for Off and On operand labels Section 3 2 2 ldcd updated the description for Off and On ope...

Page 150: ...cts in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsi...

Page 151: ...47 jcrf instruction format 47 Tab 48 jcrr instruction format 49 Tab 49 jfbkf instruction format 50 Tab 50 jfbkr instruction format 52 Tab 51 jmpf instruction format 52 Tab 52 jmpr instruction format 53 Tab 53 jocf instruction format 56 Tab 54 jocr instruction format 59 Tab 55 joidf instruction format 60 Tab 56 joidr instruction format 61 Tab 57 joslf instruction format 64 Tab 58 joslr instruction ...

Page 152: ...115 d_ls 129 Tab 116 s_hs 129 Tab 117 oax 129 Tab 118 Switch 130 Tab 119 stsrb instruction format 131 Tab 120 sub instruction format 132 Tab 121 subi instruction format 133 Tab 122 swap instruction format 134 Tab 123 swi instruction format 135 Tab 124 toc2 instruction format 136 Tab 125 toint instruction format 137 Tab 126 wait instruction format 140 Tab 127 wrspi instruction format 141 Tab 128 xo...

Page 153: ...tions 10 2 11 Control status and flags instructions 10 2 12 Intercore communication instructions 11 2 13 Shortcuts 12 2 14 Current sense blocks 12 2 15 Output drivers 13 2 16 Interrupts 14 2 16 1 Automatic interrupt 14 2 16 2 Driver disable interrupt 14 2 16 3 Software interrupt 15 2 17 Counter timers 15 2 18 SPI back door 15 3 Instruction set and subsets 16 3 1 Internal registers operand subsets ...

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