NXP Semiconductors PN7462AU Quick Start Manual Download Page 32

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NXP Semiconductors

UM10883

PN7462 family Quick Start Guide - Development Kit

UM10883

All information provided in this document is subject to legal disclaimers.

User manual
COMPANY PUBLIC

Rev. 1.6 — 14 May 2018

319816

32 of 120

5.6 Debug interface

The PNEV7462C board has SWD interface port (JP4 10-pin Cortex connector). The
LPC-Link 2 standalone debug probe connects to this interface via flat cable from J7 as
illustrated on the following picture.

Fig 34.

LPC-Link2 debug probe connected to the PNEV7462C

Summary of Contents for PN7462AU

Page 1: ...k Start Guide functional description of the customer board NFC Cockpit Abstract This document describes PN7462 Controller Development Kits It also describes PN7462 software stack gives directions to run example application using the MCUXpresso IDE Document provides PN7462 customer board configuration instructions gives board hardware overview and provides basic steps how to use NFC Cockpit applica...

Page 2: ...Reworked NFC Cockpit usage description 1 4 20170907 Updated Getting started description PN7462 plugin for MCUXpresso not needed form version 10 0 2 Reworked NFC Cockpit installation description 1 3 20170511 Development Kit description added MCUXpresso IDE support added Board description and schematic updated SW examples description updated Abbreviation section added 1 2 20170216 PNEV7462B customer...

Page 3: ...plication It is also provided extensive introduction to the PN7462 family software stack 5 and describes each example in detail Finally document describes NFC Cockpit 6 custom Windows application used in prototyping and optimization In this document the terms MIFARE DESFire card MIFARE Classic card and MIFARE Ultralight card refer either to a MIFARE DESFire IC based contactless card a MIFARE Class...

Page 4: ...nna matching 4 Sample NFC cards and tags 5 2 USB cables A to mini and A to micro 6 10 PN7462 samples 7 7 5V DC power supply 8 LPC Link 2 debug adapter OM13054 1 1 2 OM27462CDKP OM27462CDKP Development Kit is based on the PNEV7462C board Content of the Development Kit is displayed on the following picture Fig 2 OM27462CDKP Development Kit Development Kit contains 1 PNEV7462C board with standard 65x...

Page 5: ...al disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 5 of 120 7 LPC Link 2 debug adapter OM13054 1 Control Panel Hardware and Sound Devices and Printers Fig 3 Properly enumerated USB CCID reader At this point a favorite PC SC application can be started and tested with cards contained in the kit ...

Page 6: ... and used as input in design time PN7462AU FW and SW Examples available on the product page ranging from POS demo contact and contactless CCID reader P2P application NFC forum related examples are customized primarily for PNEV7462B C board and supported by MCUXpresso Keil or IAR development tools 2 2 PNEV7462B board Fig 4 PNEV7462B board The board consists of the following blocks 1 PN7462AU circui...

Page 7: ...power supply 7 5V max PN7462B v2 2 external power supply 13 5V max 2 USB supply external supply and LPC supply Fig 5 PNEV7462B supply 2 2 2 PN7462AU block The main part on the evaluation board is PN7462AU It features a 32 bit ARM Cortex M0 based NFC microcontroller offering a one chip solution to build contact and contactless applications Key features are 20 MHz Cortex M0 core 80 160 kB Flash 12 k...

Page 8: ...Fig 6 PNEV7462B board schematic PN7462 part 2 2 3 LPCXpresso block This block provides expansion interface for LPCXpresso MCU board providing standard LPCXpresso m bed expansion connector DIL54 LPCXpresso SPIM and I2CM interfaces are routed to the PN7462AU host interface selector Additionally board features a USB micro B connector X1 routed to the LPC board USB interface and the LPC board reset ci...

Page 9: ... from NXP In this use case the PN7462AU is the main controller for the electrical and protocol part for the main card slot while the secondary slots are electrically controlled by an extra contact front end interface TDA the PN7462AU being the protocol controller for these extra slots TDA8026 I2C port is connected to the PN7462 I2CM to enable IC configuration In this case several smart cards can b...

Page 10: ...ment Kit UM10883 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 10 of 120 1 2 optional SAM slots can be assembled Fig 8 PNEV7462B TDA8026 part schematics ...

Page 11: ... coil circuit itself Symmetrical coupling is used with DPC Dynamic Power Control feature of the PN7462 and offers an improved overall RF performance This requires the antenna to be symmetrically tuned and it requires the AGC to correlate with the driver current ITVDD and it requires the dynamic power control to be properly calibrated The DPC Antenna tuning symmetrical tuning with DPC combines the ...

Page 12: ...trical The antenna connection uses the standard tuning circuit Fig 10 The EMC filter is typically a second order low pass filter as shown in Fig 18 and contains an inductor L0 and a capacitor C0 The cut off frequency defines the overall detuning behavior as well as the transfer function of the antenna circuit For symmetrical DPC tuning EMC filter is designed with a cut off frequency of fEMC 14 8 M...

Page 13: ...2018 319816 13 of 120 1 The matching components might be adapted due to antenna layout changes Fig 11 Antenna and matching Table 1 lists components for the symmetric matching Table 1 Assembled matching components General component Component PNEV7462B Value Comment L0 L4 L7 470nH PNEV7462B V2 1 0603LS 471NXJBC PNEV7462B V2 2 36502AR47JTDG C0 C28 C31 100pF C0 split in 3 parallel capacitors C29 C32 2...

Page 14: ...ading and detuning might exceed the ITVDD limit if the symmetrical tuning is used This might destroy the NFC reader IC 2 2 6 2 PCB for individual antenna matching Development kit contains 3 PCB boards for individual antenna matching This boards are intended for prototyping custom asymmetrical or symmetrical DPC antenna design Default matching circuit can be replaced by individual antenna matching ...

Page 15: ...of the customer evaluation board is the replacement and latest version of the customer evaluation board incl FCC certification Functionality of the V2 2 is the same as of V2 1 Fig 13 PNEV7462B V2 2 Design changes V2 1 to V2 2 External supply maximum value increased from 7 5V to12V Different routing PNEV7462B V2 1 stays the board reference design which can be obtained from the NXP DocStore 8 Layout...

Page 16: ...PNEV7462B board It can be powered either from an external off board power supply on DC power connector from LPC USB connector X1 and from USB port on connector X3 Jumper JP41setting Fig 14 needs to be done to prepare the board for one of the power supply options Fig 14 Board Power settings 3 1 1 PN7462AU supply options The boards offer several ways of supplying the PN7462AU IC The main chip supply...

Page 17: ...ctly the following LEDs should light green 3V3 5 V and VBUS In Fig 16 the position of the three different LED s is shown Fig 16 Supply indicator 3 1 3 Supply options for PVDD VUP_TX and TVDD The PN7462AU allows different options of supplying PVDD_IN PVDDM_IN as well as for TVDD_IN and VUP_TX The default setting is to use the internal supply for PVDD as well as TVDD That means default setting is PV...

Page 18: ... default settings Fig 17 Default supply connection of the PN7462AU using all blocks To change settings the corresponding shortcut resistors marked in Fig 17 needs to be placed to the corresponding position default settings are marked in green Table 2 Supply options Supply options VUP_TX 3V3 5V VBUS EXT TVDD_IN TVDD_OUT 3V3 5V VBUS EXT PVDD_IN 3V3 PVDD_OUT PVDDM_IN 3V3 PVDD_OUT Note If PVDD is exte...

Page 19: ...ost through four pads with alternate function ATX_A ATX_B ATX_C and ATX_D The ATX pads are routed at the JP32 10 pin header according the following table Table 3 PN7462 HIF pins Pin name Description JP32 pin ATX_A HSU_RX I2C_SCL SPI_NSS 1 ATX_B HSU_TX I2C_SDA SPI_MOSI 3 ATX_C HSU_RTS_N SPI_MISO USB_DP 5 ATX_D HSU_CTS_N SPI_MOSI USB_DM 7 3 2 1 1 USB Host Interface configuration The yellow marked ju...

Page 20: ...ccording the Table 3 and additional jumper configuration is not needed 3 2 1 3 SPI Host Interface configuration The yellow marked jumpers Fig 20 needs to be set for using the SPI host interface of the chip This will connect the SPI_MOSI of the PN7462AU to the I O P0 18 SPI_MISO to the I O P0 17 SCK to the I O P0 15 and also the NSS of the PN7642AU to the I O P0 16 of the LPCXpresso board Fig 20 Ho...

Page 21: ...I O P0 1 of the LPCXpresso board extension m bed connector Fig 21 Host Interface selection HSU In case that external host needs to be connected to the PN7462 over HSUART interface then corresponding HSUART interface lines RX TX CTS RTS can be accessed directly on the JP32 according the Table 3 and additional jumper configuration is not needed 3 2 2 Debug interface The PNEV7462B board is equipped w...

Page 22: ...ion register settings can be stored in the EEPROM as well as saved in configuration file and used as input in design time PN7462AU FW and SW Examples available on the product page ranging from POS demo contact and contactless CCID reader P2P application NFC forum related examples are customized primarily for PNEV7462B C board and supported by MCUXpresso Keil or IAR development tools 4 2 PNEV7462C ...

Page 23: ...External but for the best performance external power source is recommended Fig 24 PNEV7462C supply 4 2 2 PN7462AU block The main part on the evaluation board is PN7462AU It features a 32 bit ARM Cortex M0 based NFC microcontroller offering a one chip solution to build contact and contactless applications Key features are 20 MHz Cortex M0 core 80 160 kB Flash 12 kB RAM 4 kB EEPROM State of the art ...

Page 24: ...2AU block 4 2 3 Smartcard interface The PN7462AU integrates contact interface to enable communication with ISO7816 and EMVCo contact smart cards without the need for an external contact front end It offers a high level of security for the cards by performing current limitation short circuit detection ESD protection as well as supply supervision Card slot contactor is located on the board bottom si...

Page 25: ...l circuit itself Symmetrical coupling is used with DPC Dynamic Power Control feature of the PN7462AU and offers an improved overall RF performance This requires the antenna to be symmetrically tuned and it requires the AGC to correlate with the driver current ITVDD and it requires the dynamic power control to be properly calibrated The DPC Antenna tuning symmetrical tuning with DPC combines the ad...

Page 26: ...trical The antenna connection uses the standard tuning circuit Fig 10 The EMC filter is typically a second order low pass filter as shown in Fig 18 and contains an inductor L0 and a capacitor C0 The cut off frequency defines the overall detuning behavior as well as the transfer function of the antenna circuit For symmetrical DPC tuning EMC filter is designed with a cut off frequency of fEMC 14 8 M...

Page 27: ... COMPANY PUBLIC Rev 1 6 14 May 2018 319816 27 of 120 5 The matching components might be adapted due to antenna layout changes Fig 29 Antenna and matching Table 1 lists components for the symmetric matching Table 1 Assembled matching components General component Component PNEV7462C Value Comment L0 L4 L7 470nH 36502AR47JTDG C0 C28 C31 100pF C0 split in 3 parallel capacitors C29 C32 27pF C38 C44 120...

Page 28: ...C37 C47 1pF C21 C40 C46 120pF C22 C41 C43 68pF Rs R117 R119 2 2Ω Rs split in 2 parallel resistors R118 R120 2 2Ω Note Without proper DPC calibration the loading and detuning might exceed the ITVDD limit if the symmetrical tuning is used This might destroy the NFC reader IC 4 2 4 2 PCB for individual antenna matching Development kit contains 3 PCB boards for individual antenna matching This boards ...

Page 29: ...port on connector X3 Jumper JP2 setting Fig 30 needs to be done to select the power source 1 External power supply selected 2 USB power supply selected Fig 30 PNEV7462C board power source configuration 5 2 PN7462AU IC power supply options The PN7462AU IC main supply voltage input of the microcontroller VBUS can be configured to 5V 3 3 V or USB by setting theVBUS jumper as described in Fig 31 1 VBU...

Page 30: ...and resistor jumper R181 and R179 placed If external 3V3 supply is needed then R179 and R181 needs to be removed JP42 closed to turn off internal LDO and 3V3 directly soldered to the R179 and R181 pads marked red Fig 33 5 4 2 Supply options for VUP_TX Internal contactless TX LDO is by default supplied from on board 5V LDO In this case resistor jumper R213 is placed and R188 removed To supply VUP_T...

Page 31: ...ts interfacing one out of the four different host at the time USB 2 0 full speed with USB 3 0 hub connection capability HSUART for serial communication supporting standards speeds from 9600 bit s to 115200 bit s and faster speed up to 1 288 Mbit s SPI with half duplex and full duplex capability with speeds up to 7 Mbit s I2C supporting standard mode fast mode and high speed mode with multiple addr...

Page 32: ...V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 32 of 120 5 6 Debug interface The PNEV7462C board has SWD interface port JP4 10 pin Cortex connector The LPC Link 2 standalone debug probe connects to this interface via flat cable from J7 as illustrated on the following picture Fig 34 LPC Link2 debug probe connected to the PNEV7462C ...

Page 33: ...nds to the VCOM port and dedicated firmware executes commands on the hardware level An optional part of the same firmware binary is also the Secondary Firmware application typically featuring some dedicated compliance test application that needs to meet specific time constraints for example EMVCo loopback The Secondary application can be started and stopped trough the NFC cockpit GUI from the prim...

Page 34: ...eld 1 0x6A Get Application ID command of MIFARE DESFire EV1 Fig 35 NFC Cockpit activation of a MIFARE DESFire EV1 card Get Application ID Similar functionality does exist for ISO IEC 14443 A and B for NFC type F for ISO IEC 15693 and I Code ILT communication Be aware that a LOAD_RF_CONFIG command must be executed manually before the corresponding protocol settings are loaded from the EEPROM into t...

Page 35: ...62AU register On mouse over the application displays a short description of the register parts Note Some register content cannot be changed manually read only and some content might be overwritten by the PN7462 family firmware 1 Register area is a RAM area i e might be overwritten or changed automatically Fig 36 PN7462 NFC cockpit register access All registers which are used in the LOAD_RF_CONFIG ...

Page 36: ...e PN7462 family IC EEPROM into a binary file This can be used to generate a backup of all settings or to transfer optimized settings onto another board or into own software Load EEPROM loads a binary file and stores it into the user area of the PN7462 family IC EEPROM Fig 37 PN7462 family IC direct EEPROM access 6 7 PN7462 family IC internal test bus The NFC cockpit allows to use the PN7462 family...

Page 37: ...and digital test signals The analog test signals can be directly selected at GPIO1 and 2 For the digital test signals GPIO4 and 5 can be used Afterwards a click on the Route Test Signal button activates the chosen signals 6 8 PN7462 family Dynamic Power Control The DPC tab provides the functionality to easily perform a correlation test a DPC calibration and the DPC trimming see Fig 39 The detailed...

Page 38: ...alled Adaptive Wave Control AWC The NFC Cockpit provides a AWC functionality to allow an easy optimization of the shaping functions see Fig 40 Requirement a properly tuned antenna is connected and the DPC is calibrated Note It is recommended to disable the AWC before starting the AWC function in the NFC Cockpit to avoid confusion the AWC itself is done inside the PN7462 FW and the NFC cockpit trie...

Page 39: ...te the antenna in gear 0 unloaded Load Protocol for e g Type A 106 and enable RF field RF Field On Step 3 Start Endless and watch the current gear must be 0 Step 4 Check the pulse shape with a Reference PICC and an oscilloscope Move the sliders TAU MOD FALLING TAU MOD RISING and TX RESIDUAL CARRIER to optimize the shaping Step 5 Note down the optimum settings and save the corresponding register se...

Page 40: ...rites the new AWC data into the look up table in the PN7462 EEPROM Step 10 Load Protocol with the same protocol e g Type A 106 and then send single or endless REQA Check the wave shape in all gear positions 6 10 PN7462 family Rx Matrix test The receiver settings of the PN7462 family IC normally need to be optimized to achieve the best performance This optimization can be done manually using the te...

Page 41: ...n easy solution is the Rx Matrix Test This tool simply tries each combination of settings and reports the number of proper receptions 6 10 2 Rx Matrix test principle The Rx matrix controls the PNEV7462B evaluation board and allows to configure Free number of trials per register combination Free number and combination of register bits Free limit of minimum and maximum value Free choice of protocol ...

Page 42: ...x The test result is stored as table when the test is finished The table can be opened with e g Microsoft Excel for interpretation View Output 6 10 3 Rx Matrix XML input file The Rx Matrix Test requires the input configuration in an XML file A few example XML files for type A B F 15693 and I Code ILT are part of the NFC Cockpit package c nxp NxpNfcCockpit_v VERSION cfg RxMatrix RxMatrix_PN7462AU R...

Page 43: ...k certain bytes for e g the PUPI in the card response 0x00 0x00 Bytes to be received These bytes are checked as Rx data 0x44 0x03 Optional if AWG is connected VoltageLevel minValueInmV 100 maxValueInmV 2000 stepSizeInmV 500 Defines the LMA voltage level of the AWG from minimum to maximum value with given step size Register settings Parameter name Rx Gain minValue 0x01 maxValue 0x03 registerAddress...

Page 44: ... As a prerequisite the USB driver and National Instruments VISA driver package 14 have to be installed Remark This NI VISA version does not conflict with the CTC Advanced WavePlayer tool Make sure that the NET development support is installed as shown in Fig 43 1 Install the NET IVI development support Fig 43 NI VISA installation 6 11 2 AWG setup and test for type A 106 The Fig 44 shows a typical ...

Page 45: ...the peak voltage level of the LMA the LMA output toggles between 0V and the defined amplitude The AWG output can directly drive a Reference PICC modulation input Note EMVCo LMA levels normally are in the range of 700 800 mV for minimum LMA test in operating Volume 1 For compliance test it is recommended to use a calibrated reference tool like e g the CTC Advanced WavePlayer The PICC response itsel...

Page 46: ...p the hardware as shown in Fig 42 Place the Reference PICC close to the PCD antenna Step 2 Setup the AWG in the NFC Cockpit as defined above Step 3 Enable the test bus and route TX_IRQ to a test pin e g IRQ pin Step 4 Load Protocol with type A 106 and enable the RF Field Step 5 Send a single REQA the ATQA should be received properly Note After loading the settings and the sequence into the AWG the...

Page 47: ...tage level of the LMA the LMA output toggles between 0V and the defined amplitude The AWG output can directly drive a Reference PICC modulation input Note EMVCo LMA levels normally are in the range of 700 800 mV for minimum LMA test in operating Volume 1 For compliance test it is recommended to use a calibrated reference tool like e g the CTC Advanced WavePlayer The PICC response itself can be def...

Page 48: ... Place the Reference PICC close to the PCD antenna Step 2 Setup the AWG in the NFC Cockpit as defined above Step 3 Enable the test bus and route TX_IRQ to a test pin e g IRQ pin Step 4 Load Protocol with type B 106 and enable the RF Field Step 5 Send a single REQB the ATQB should be received properly Note After loading the settings and the sequence into the AWG the AWG can be switched to local con...

Page 49: ...uch a test run to indicate the sensitivity limit with RxGain 2 HPCF 2 MinLevel 3 and MinLevel 6 1 The graph shows pass rate versus LMA input level Reference PICC 2 With RxGain 2 the performance is less than optimum Fig 47 Rx Matrix Result example with AWG 6 12 PN7462 family Low Power Card Detection The NFC Cockpit allows the configuration and test of the Low Power Card Detection LPCD of the PN7462...

Page 50: ...plication for EMVCo L1 certification The EMVco Loopback or other application can be started by pressing the Start Secondary Firmware button and the function can be stopped by pressing the Stop Secondary Firmware button Fig 49 PN7462 family FW tab with EMVCo Loopback function 6 14 PN7462 family Scripting The NFC Cockpit allows to use a simple script language to program own scripts for test purpose ...

Page 51: ...tomers to create their own contact and contactless software stack and applications for the PN7462 Family 5 This API facilitates all operations and commands required in contact and contactless applications such as reading or writing data to cards or tags exchanging data with other NFC enabled devices or allowing NFC reader ICs to emulate cards as well The PN7462 family software application stack co...

Page 52: ...t till one or more expected events occurs from the HW CLIF HAL CT HAL I2CM SPIM HAL 3 Non blocking functions functions configuring the HW and expect one or more events but don t wait till it occurs The events are notified to the caller of the function Timer Host interface The HW ISR handles HW events interrupts and signals of the blocking functions or notifies non blocking functions The HW ISR als...

Page 53: ...t protocol library implements the components for the contactless protocol such as EMV ATR Parser T 0 protocol T 1 protocol This library also handles the timing compliance violations 7 3 Application layer AL In the application layer customer applications shall be implemented and can directly use HAL APIs or APIs from the PAL libraries The contactless example or application is either NFC Forum Polli...

Page 54: ...d in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 54 of 120 7 5 Component view 7 5 1 Contactless component view In contactless component view Fig 52 for the phExMain example is shown Fig 52 Contactless architecture view ...

Page 55: ...w 7 6 Building a project from bottom to top In order to use the PN7462 family firmware a stack of components has to be initialized from bottom to top Every component in the software stack has to be initialized before it can be used The referred initialization of each layer generates a data context which feeds the immediate upper layer Some of the components may need a data context coming from the ...

Page 56: ...ge queues which are used to communicate between the tasks The tasks can wait for the messages and if not available scheduler suspends these tasks which are waiting and allow the other tasks to run The FreeRTOS provides the events which are used to communicate inside the tasks The tasks can go to suspended state waiting for the events as well Whenever the events occur the scheduler wakes up that pa...

Page 57: ...t environment For developing PN7462 family firmware and customer applications all components listed in the Table 6 are required Table 6 Development environment Item Version Purpose PNEV7462B or PNEV7462C 2 1 2 2 or 1 0 Engineering development board LPC Link 2 1 0 2 0 Standalone debug probe MCUXpresso IDE 10 0 2 Development IDE PN7462AU FW and SW examples 5 12 00 Installer package Fig 56 gives gene...

Page 58: ...elopment boards with debug probes from NXP P E and SEGGER Available in full featured free code size unlimited and affordable professional editions including MCUXpresso IDE email support and advanced trace features This tool can freely be downloaded from the MCUXpresso website 0 Before one can download the software it is necessary to create an account Creating an account is absolutely free If a Pro...

Page 59: ...FW and SW examples package The PN7462 FW and SW examples are provided as a Windows installer package available on the product page or through the NXP DocStore 8 It is assumed that examples are installed on development PC The archive file containing SW and FW examples is located in the install directory NXP Semiconductors PN7462AUPspPackageFull vXX_XX_XX PN7462AU Software folder 8 4 Updating PN7462...

Page 60: ...he most commonly used features of the MCUXpresso IDE Quickstart Panel easies importing creating building and debugging projects Project import consists of following steps Start the MCUXpresso IDE and select new workspace Select the option Import project s see picture below Browse to the software package zip archive MCUXpresso unzips the software package The software package is ready for use Fig 60...

Page 61: ...0883 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 61 of 120 Fig 61 Importing project to MCUXpresso IDE 2 Browse to the PN7462AU FW_vXX XX XX_Full zip and click Next ...

Page 62: ...ject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 62 of 120 Fig 62 Select project Select projects to be imported and then click Finish Selected examples will be imported to the workspace When the import process is finished the development and editing the code can start ...

Page 63: ... May 2018 319816 63 of 120 Fig 63 Project Workspace with all examples 8 6 Building projects Building projects in a workspace can be started trough Quickstart Panel Build all projects command Alternatively a single project can be selected in the Project Explorer View and built separately Note that building a single project may also start a build of any associated library projects The project can be...

Page 64: ...2018 319816 64 of 120 Fig 64 Building a project As a part of the build process the binary file for flash in AXF format is created This binary file can be used to update PN7462AU flash via USB mass storage interface or by using flash tool or debug in MCUXpresso IDE In case that Binaries folder is not visible in the project structure refresh the project right click on project and select Refresh Fig ...

Page 65: ... click Edit selected project project settings Build result can be monitored on the build console Successful build Fig 66 Fig 66 Successful build 8 7 Running and debugging the example projects This description shows how to run the PN7462AU PN7462AU_ex_phExMain example application for the PN7462AU customer development board in debug mode The same basic principles will apply for all other examples In...

Page 66: ...ownloaded to the target and it s programmed to the flash memory a default breakpoint is set on the first instruction in main the application is started by simulating a processor reset and code is executed until the default breakpoint is hit To start debugging your application on the PN7462AU simply highlight the project in the Project Explorer and then in the Quick start Panel click Debug as shown...

Page 67: ...uide Development Kit UM10883 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 67 of 120 Fig 68 Launch debug session Fig 69 Selecting debug probe ...

Page 68: ...10883 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 68 of 120 Fig 70 Project debugging After the software upload the execution of the application starts immediately ...

Page 69: ...XP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 69 of 120 8 7 1 Break points PN7462AU supports 4 breakpoints and 2 watch points In usual way double click on the left vertical editor strip to set the break points The execution of the application will be stopped when the break point is reached Fig 71 Inserting breakpoints ...

Page 70: ...ll information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 70 of 120 8 7 2 Debug traces The debug traces can be seen on console as shown in Fig 72 Fig 72 Debug view and debugger traces ...

Page 71: ...14 May 2018 319816 71 of 120 8 7 3 Peripheral view MCUXpresso IDE provides direct access to all the peripheral registers of the PN7462AU To see the peripheral registers follow the steps as shown below 1 Go to Window Show view Other 2 Select Peripherals Fig 73 Peripheral view Select the appropriate register or IP to watch or change the register values As shown below we see the fields and descriptio...

Page 72: ...rmation provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 72 of 120 1 Select the relevant peripheral 2 Register bit fields and description in the relevant view Fig 74 PN7462AU EECTRL peripheral view ...

Page 73: ...SB MSD 8 9 Updating flash EEPROM via SWD interface Ensure that LPC Link2 is connected to PNEV7462B board see Fig 75 and follow the steps below Fig 75 HW setup for the flashing via LPC Link 2 Click icon Fig 76 on the menu bar to start LinkServer GUI Flash programmer tool Fig 76 Starting flash tool in MCUXpresso Once the flash tool started the correct connection and flash driver file needs to be spe...

Page 74: ... V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 74 of 120 1 Select conection script flash driver and binary file 2 Ensure that all the options are set properly and click OK Fig 77 Build output flash binary file After selecting binary file flash process starts and report is shown 3 Flash report appears Fig 78 Program flash report ...

Page 75: ...face primary download mode To mount a PNEV7462B C as a USB Mass storage drive 1 Ensure that HIF selection is USB see Fig 79 to be skipped with PNEV7462C board 2 USB Port of the PC running Windows OS is connected to the micro USB port labelled X3 on the PNEV7462B 3 Press RST_N switch Press DWL_REQ switch 4 Release RST_N and keep holding DWL_REQ 5 Release DWL_REQ button after about two seconds Fig 7...

Page 76: ...0 Read and write allowed 01 Cannot read Write allowed Only applicable sectors erased before writing 02 Cannot read All sectors of the applicable memory are erased before writing 03 Cannot read Cannot write via USB mass storage Table 9 Status of read write operating code s Description 0 Last write operation was successful 1 Memory region formatted 2 or anything else Failed 3 Fresh memory FLASH EEPR...

Page 77: ...upporting debug messages printouts via the LPC Link 2 debug probe directly to the MCUXpresso IDE console The LPC Link 2 probe needs to be connected to the board Fig 75 Debug build configuration enables printout of application messages Printout messages are displayed in the Debug Messages Console View Console view can be opened in menu Window Show View Console or by clicking the shortcut keys Alt S...

Page 78: ...ion and reauthentication for MIFARE Classic and inventory read command for ICODE SLIX Since Inventory read is a manufacturer specific proprietary command thus inventory read will work only for NXP manufactured ICODE cards one of which is ICODE SLIX Supports Topaz Jewel Tags Command supported RID READ8 WRITE NE8 2 Peer to peer mode Supports Active F 212 till PSL request only Supports Passive A 106 ...

Page 79: ...face Yes NXP NFC Reader Library Yes CT Reader Library Yes FreeRTOS Yes Non RTOS Yes Standby mode Yes HIF MIF Interface No 9 2 3 FreeRTOS usage in this example Example can be built in two configuration modes with FreeRTOS and without FreeRTOS support By setting precompile directive PHFL_HALAPI_WITH_RTOS or PHFL_HALAPI_NO_RTOS the mode of the configuration is specified To build example in one or ano...

Page 80: ...nabled The standby feature can be enabled disabled at compile time with the precompile directive To enable standby mode PHFL_ENABLED_STANDBY directive needs to be uncomment and can be found in the APP_NxpBuild h file In this configuration the FW by default puts the IC to standby and enables the wakeup sources such as contact card presence wakeup timer and RF level detector only for listen mode The...

Page 81: ... Quick Start Guide Development Kit UM10883 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 81 of 120 Fig 83 phExMain standby flow ...

Page 82: ...y If a Type A card is detected with SAK of 0x8 1K MIFARE Classic card or 0x18 4K MIFARE Classic card then the MIFARE Classic example is executed The example performs initial authentication of block X and then reads write to this sector Further the example performs authentication of another block say X 1 using the session key established during initial authentication this is called re authenticatio...

Page 83: ... is 0x20 expected card is MIFARE DESFire EV1 then ISO14443 4 Type A reader example is executed The MIFARE DESFire example implements L4 exchange of GetVersion command at 106 212 424 and 848 kbps No other commands are currently exchanged as they require authentication and crypto operations which are not currently supported in the release Supported functionality 1 Get Version at 106 212 424 848 kbps...

Page 84: ...cuted This example is used demonstrate the ISO144434 exchange of APDUs to a Type B card at all baud rates Supported functionality 1 Get Challenge106 212 424 848 kbps 2 No encryption Implementation in the phExMain_TypeB_L4Exchange c file 9 2 12 Type F FeliCa tag This example is used to read and write FeliCa frames to FeliCa tags at 212 424 kbps Since the stack supports Type 3 tags check is performe...

Page 85: ...onfiguration is done via define macro in phExMain_Clif h If the SAK is 0x40 discovery loop detects peer ISO18092 initiator the phExMain_PasTgt is executed that responds to ATR_REQ from the initiator This example further waits for a NFC DEP frame from the initiator 9 2 16 Contact Example If the IC boots because of CT presence wakeup reason or if the CT presence interrupt is generated the System tas...

Page 86: ... mode of discovery loop d If boot reason is RFLD or external RF is detected perform listen mode of discovery loop e Notify system task if polling listening is completed and standby is enabled 3 CT task a Enable CT presence interrupt and wait for CT presence interrupt b If boot reason is CT presence or CT presence interrupt is detected perform CT example c Notify system task if polling listening is...

Page 87: ...elopment Kit UM10883 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 87 of 120 Fig 85 PN7462AU phExMain sequence diagram for standby scenario with RTOS ...

Page 88: ...C Rev 1 6 14 May 2018 319816 88 of 120 Fig 86 PN7462AU phExMain sequence diagram for non standby scenario with RTOS 9 2 18 No RTOS management In case of No RTOS the entry point from flash boot is phExMain_NoRTOS The functionality remains the same except that the CLIF example and the CT examples are called from a single executive while loop based on timer interrupt or external RF detection or CT pr...

Page 89: ... transaction Application is based on the NFC Reader Library CT Library and be run with or without FreeRTOS 9 3 1 Demo setup This section describes in detail the setup and execution environment required for the phExEMVCo application The following things are required for setup 1 PNEV7462B C board 2 LPC Link 2 board 3 Power adapter 4 Contact and contactless EMVCo card Externalpower supply LPC LINK2 F...

Page 90: ...e present in the POS for EMV transaction Low Power Card Detection LPCD is disabled in this profile 9 3 4 EMV transaction This example implements next EMV Transactions SELECT PPSE SELECT command GET PROCESSING OPTIONS READ RECORD GENERATE AC Supported EMV functionality ATR Parsing accordingly to the EMV specifications Send Different AIDs to identify card Master Card Credit or Debit Visa Card Credit...

Page 91: ...le with the only difference that for the transaction static predefined packets are used Application does not implement CT and Standby functionality and it is not based on the FreeRTOS 9 4 1 Demo setup This section describes in detail the setup and execution environment required for phExRf application The following devices are required to run the example 1 PNEV7462B C board 2 LPC Link2 board 3 Powe...

Page 92: ...isclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 92 of 120 Feature supported NXP NFC Reader Library No CT Reader Library No FreeRTOS No Non RTOS Yes Standby mode No HIF MIF Interface No 9 4 3 Application Flow The figure below demonstrates the application flow Fig 89 phExRF Example Application Flow ...

Page 93: ...cards Application use only HAL APIs and perform same CTIF functionality as 0 phExMain example with the only difference that for the transaction static predefined packets are used and example is not using any library phExCt performs activation of an EMVCo card SELECT Master card APDU is sent depending on the protocol supported by the card and expects RAPDU 0x90 0x00 The example is also capable of d...

Page 94: ...ed User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 94 of 120 9 6 2 Features phExCT example is covering next features Table 13 phExRf Example features Feature supported CLIF Interface No CT Interface Yes NXP NFC Reader Library No CT Pal Library No FreeRTOS No Non RTOS Yes Standby mode No HIF MIF Interface No 9 6 3 Application Flow The figure below demonstrates the application flow ...

Page 95: ...V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 95 of 120 Fig 91 phExCT Example Application Flow 9 6 4 EMVCo activation The example performs EMVCo activation and EMVCo ATR parsing It also determines the protocol supported by the card 9 6 5 SELECT master card The example sends a SELECT master card APDU and expects a RAPDU 0x90 0x00 ...

Page 96: ...tionality and it is not based on the FreeRTOS 9 7 1 Demo setup In this example the same setup is used as in phExEMVCo example 9 7 2 Features phExCT example is covering next features Table 14 phExRf Example features Feature supported CLIF Interface No CT Interface Yes NXP NFC Reader Library No CT Pal Library Yes FreeRTOS No Non RTOS Yes Standby mode No HIF MIF Interface No 9 7 3 EMVCo activation Th...

Page 97: ...ctions deactivation is performed Application does not implement CLIF and Standby functionality and it is not based on the FreeRTOS 9 8 1 Demo setup In this example the same setup is used as in phExMain example 9 8 2 Features phExCT7816 example is covering next features Table 15 phExCT7816 Example features Feature supported CLIF Interface No CT Interface Yes NXP NFC Reader Library No CT Pal Library...

Page 98: ...rface Frames FREE Format is used Application is implementing CT functionality with SPI Host interface and it is not based on the FreeRTOS Setup consist of two projects HIF application executing on the PN7462AU and the LPC application executing on the LPC1769 board LPCXpresso board for LPC1769 with CMSIS DAP probe 9 LPC project is in the archive file install directory NXP Semiconductors PN7462AUPsp...

Page 99: ...y of this example has to be executed GPIO6 7 8 It is also used to select the host interface or master interface to be used GPIO4 5 For each different functionality a different MCUXpresso project is required for LPC1769 side while PN7462AU is running the phExHif MCUXpresso project The phExHIF indicates its readiness to LPC1769 through GPIO1 of PN7462AU connected to GPIO0 0 of LPC1769 APP ready pin ...

Page 100: ... 1 6 14 May 2018 319816 100 of 120 1 IRQ line VIA marked yellow 2 An additional wire should be solder on this VIA to make the IRQ line accessible Fig 93 PNEV7462C IRQ pin 9 9 2 Features phExHif example is covering next features Table 16 phExHif Example features Feature supported CLIF Interface No CT Interface Yes NXP NFC Reader Library No CT Pal Library Yes FreeRTOS No Non RTOS Yes Standby mode No...

Page 101: ...AU GPIO2 3_LPC GPIO6_PN7462AU GPIO2 4_LPC Chosen HIF 0 0 0 Loopback on HIF 0 0 1 Forward HIF Rx Packet to I2CM Tx 0 1 0 Forward HIF Rx Packet to SPIM Tx 0 1 1 Forward HIF Rx Packet to SPIM I2CM Tx Both 1 0 0 Program EEP with HIF Rx Packet 1 0 1 Program FLASH with HIF Rx Packet 1 1 0 Forward HIF Rx Packet to CT 1 1 1 RFU Application ready PIN is connected with GPIO0 0_LPC on the LPC board Important...

Page 102: ... Development Kit UM10883 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 6 14 May 2018 319816 102 of 120 Boot EEPROM Boot FLASH Boot CT Boot GPIO HW I2CM HW SPIM HW HIF ...

Page 103: ...lpc17xx_lib CMSISv2p00_LPC17xx 9 10 PN7462AU_ex_phExPos POS use case demo application shows how to use PN7462AU in combination with second application hosted on the µController PNEV7462B board is supported PNEV7462C is supported with HW modifications as described in 9 9 1 In this example LPC1769 µC is used and connection is established through SPI host interface POS use case demonstrate the Pay pa...

Page 104: ...n LPC1769 and PN7462AU Interrupt pin is used to notify valid ISO 14443 4 card to LPC1769 Note Detailed description and how to use example is described in POS Use Case Demo Setup Manual Fig 95 POS demo architecture 9 11 PN7462AU_ex_phExCcid The PC USB reader application demonstrate how to use the PN7462AU customer demo board as a CCID reader and shows how connected PN7462AU via USB interface to a P...

Page 105: ...lass is implemented in the PN7462AU The default CCID driver present in PC with Windows OS is used for operation Fig 97 Example architecture Note Detailed description and how to use example is described in PC Reader Demo Setup Manual 9 12 PN7462AU_ex_phSystemServices This example application demonstrates system services invocation The PN7462AU provides ROM services that are accessible via flash API...

Page 106: ...ng the flash results in hard fault Once SECROW functionality is locked this feature cannot be used anymore Block SWD debugging This command disables PN7462AU SWD debug interface When the PN7462AU IC is delivered from production to user the default SWD access level enables the user to view and debug user flash memory user EEPROM memory user RAM memory and peripheral registers The access level can b...

Page 107: ...tered by the terminal emulation program Each command is one character long a T command character T example application enters Type A detection mode and the terminal output is as follows Poll command received Entering TypeA Polling mode Type A Polling Type A Polling Card UID 0424566AF13B80 Card UID 0424566AF13B80 Card UID 0424566AF13B80 Type A Polling Type A Polling LED8 10 lit in circular pattern ...

Page 108: ...he card The type of the card UID and data are sent via HSU and printed on the PC console P2P functionality is integrated When a NFC enabled phone is detected from the RF field as an active or passive target the LLCP SNEP will be activated and NDEF message will be sent to the mobile device If LPCD Low Power Card Detection is enabled the reader checks during the wakeup time the presence of a card an...

Page 109: ...of data will be read from the card Note Detailed description and how to use example is described in Door Access User Manual This example is available only with PSP package from NXP DocStore 8 9 16 PN7462AU_ex_phExNFCCcid The NFC CCID is versatile demo application that features Card detection for TypeA TypeB Felica ISO15693 ISO18000p3m3 technologies Support for proprietary commands for MIFARE Class...

Page 110: ...elected proceed for File Operations APP Created By NxpNfcRdLib_v4 030 00 011627_2016 Value Len 4 0D 00 00 00 Operation successful Please remove the card Note This example is available only with PSP package from NXP DocStore 8 9 18 PN7462AU_ex_phExRfPCDA This example demonstrates simple low level API usage to perform detection anti collision activation authentication and R W operation on the Type A...

Page 111: ... EEPROM Electrically Erasable Programmable Read Only Memory FW Firmware GPIO General Purpose Input Output HAL Hardware Abstraction Layer HSU High Speed UART HW Hardware LDO Low Drop Out MSD Mass Storage Device NFC Near Field Communication P2P Peer to Peer PCB Printed Circuit Board PAL Protocol Abstraction Layer PMU Power Management Unit PSP Product Support Package RF Radio Frequency ROM Read Only ...

Page 112: ... HPCF minValue 0x00 maxValue 0x03 registerAddress 0x40004110 bitPosition 2 bitLength 2 Parameter name MinLevel minValue 0x00 maxValue 0x03 registerAddress 0x400040b4 bitPosition 12 bitLength 4 Test 11 2 Type B example with AWG control xml version 1 0 encoding UTF 8 standalone no DOCTYPE Test SYSTEM NNC_RxMatrix_Pn7462AU dtd This is an example of a TypeB test script for Pn7462AU where we acess bit ...

Page 113: ...s www nxp com docs en user guide UM10913 pdf 6 NFC COCKPIT NFC Cockpit configuration tool for NFC ICs http www nxp com products NFC COCKPIT 7 AN11706 PN7462 Antenna design guide https www nxp com docs en application note AN11706 pdf 8 NXP DocStore https www docstore nxp com 9 LPCXpresso board for LPC1769 with CMSIS DAP probe http www nxp com products OM13085 10 Dynamic Power Control https www nxp ...

Page 114: ...nimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and...

Page 115: ...ault power supply setting 31 Fig 34 LPC Link2 debug probe connected to the PNEV7462C 32 Fig 35 NFC Cockpit activation of a MIFARE DESFire EV1 card Get Application ID 34 Fig 36 PN7462 NFC cockpit register access 35 Fig 37 PN7462 family IC direct EEPROM access 36 Fig 38 PN7462 family IC analog and digital test signals 37 Fig 39 PN7462 family IC DPC 38 Fig 40 PN7462 family IC AWC 39 Fig 41 Basic Rx M...

Page 116: ... example 79 Fig 83 phExMain standby flow 81 Fig 84 phExMain non standby flow 82 Fig 85 PN7462AU phExMain sequence diagram for standby scenario with RTOS 87 Fig 86 PN7462AU phExMain sequence diagram for non standby scenario with RTOS 88 Fig 87 HW Setup for the phExEMVCo example 89 Fig 88 HW setup for the phExRF example 91 Fig 89 phExRF Example Application Flow 92 Fig 90 HW setup for the phExCT exam...

Page 117: ...3 Test input 42 Table 4 Send Data input 43 Table 5 Read Data input 43 Table 6 Development environment 57 Table 7 Files found in USB mass storage 76 Table 8 Code and data protection level 76 Table 9 Status of read write operating code 76 Table 10 phExMain Example features 79 Table 11 phExEMVCo Example features 89 Table 12 phExRf Example features 91 Table 13 phExRf Example features 94 Table 14 phExR...

Page 118: ... Host Interface configuration 20 3 2 1 4 HSUART Interface configuration 21 3 2 2 Debug interface 21 4 Hardware overview of the PNEV7462C board 22 4 1 PNEV7462C board concept 22 4 2 PNEV7462C board overview 22 4 2 1 Power circuitry 23 4 2 2 PN7462AU block 23 4 2 3 Smartcard interface 24 4 2 4 Antenna coil and related matching circuit 25 4 2 4 1 Default board antenna 25 4 2 4 2 PCB for individual an...

Page 119: ...firmware flash and EEPROM memory 73 8 9 Updating flash EEPROM via SWD interface 73 8 10 Updating flash and EEPROM via USB MSD interface 75 9 PN7462AU software examples 77 9 1 General overview 77 9 1 1 Application messages debug printouts 77 9 1 2 LEDs status specifications 77 9 2 PN7462AU_ex_phExMain CLIF CTIF functionality 78 9 2 1 Demo setup 78 9 2 2 Features 79 9 2 3 FreeRTOS usage in this exam...

Page 120: ...up 98 9 9 2 Features 100 9 9 3 HIF selection 101 9 9 4 Operation selection 101 9 9 5 EEPROM configuration dependencies 101 9 9 6 MCUXpresso projects provided for LPC1769 103 9 10 PN7462AU_ex_phExPos 103 9 11 PN7462AU_ex_phExCcid 104 9 12 PN7462AU_ex_phSystemServices 105 9 13 PN7462AU_ex_phExVCom 107 9 13 1 Demo setup 107 9 13 2 Command sets 107 9 14 PN7462AU_ex_phExDoorAccess 107 9 15 PN7462AU_ex_...

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