NXP Semiconductors PN7360AUEV, User Manual

Page: 64 / 345

NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC Rev. 1.4 — 14 May 2018
314514
64 of 345
Bit Symbol Access Value Description
6 XTAL_VOLTAGE_MUX_CLOC
K R/W 0x00
controls XTAL voltage Mux
5 XTAL_SEL_EXTERNAL_CLOC
K R/W 0x00 Controls XTAL external clock selection if
XTAL_CONTROL_SW='1'
1: Select External clock
0: Select XTAL Oscillator clock
4 XTAL_ENABLE R/W 0x00 controls XTAL Enable if XTAL_CONTROL_SW='1'
1: Enable for XTAL oscillator
0: Disable XTAL Oscillator
3 XTAL_ENABLE_KICK R/W 0x00 Controls XTAL Enable Kick if XTAL_CONTROL_SW='1'
1: Enable Kick of XTAL Oscillator
2 XTAL_BYPASS R/W 0x00 controls XTAL Bypass if XTAL_CONTROL_SW='1'
1: Bypass XTAL
0: XTAL not Bypassed
1 XTAL_CONTROL_SW R/W 0x00 high to control the XTAL oscillator by SW
1: Enable software control of XTAL oscillator
0: Disable software control of XTAL oscillator
0 HFO_ENABLE R/W 0x01 enables the HFO (activated by default)
1: Enable HFO
0: Disable HFO
7.5.1.2 HFO Trimming Value Register
Table 55. CLKGEN_HFO_TRIMM_REG (address 0008h)
Bit Symbol Access Value Description
31:5 RESERVED R/W 0x00 Reserved
4:0 HFO_TRIMM R/W 0x00 HFO trimming values
7.6 USB PLL register description
The USB PLL is controlled by the registers shown in Table 56 . Writes to any unused bits
are ignored.
Warning: Improper setting of USB PLL values may result in incorrect operation of
the USB.
Table 56. USB PLL Registers
Name Address
offset Width
(bits) Access Reset value Description
CLKGEN_USB_PLL_CONTROL_
REG 000Ch 32 R/W 00F90001h PLL global control register
CLKGEN_USB_PLL_MDEC_WO_
SOFTDEC_REG 0010h 32 R/W 00000000h PLL M decoded divider ratio
when the soft decoder is not used