NXP Semiconductors PN7360AUEV, User Manual

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NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC Rev. 1.4 — 14 May 2018
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Bit Symbol Access Value Description
Acknowledged
0: No feedback divider ratio change
1 USB_PLL_LOCK_OVERRIDEN R 0 USB_PLL lock overriden status
1: CLKGEN_STATUS_REG.USB_PLL_lock or
CLKGEN_USB_PLL_GLOBAL_CONTROL_REG.USB_
PLL_lock_bypass is high.
0: USB PLL Lock is not set
0 USB_PLL_LOCK R 0 USB_PLL lock status
1: USB PLL lock set
0: USB PLL lock is not set
7.5.1 Oscillators register description
Oscillators are controlled by the registers shown in Table 53 . More detailed descriptions
follow. Writes to any unused bits are ignored.
Table 53. Oscillators Registers
Name Address
offset Width
(bits) Access Reset value Description
CLKGEN_HFO_XTAL_REG 0004h 32 R/W 00FFF001h HFO and XTAL control register
CLKGEN_HFO_TRIM_REG 0008h 32 R/W 00000000h HFO trimming value register
7.5.1.1 HFO and XTAL control register
The CLKGEN_HFO_XTAL_REG register contains the bits that Activate/Enable XTAL,
enable HFO.
Table 54. CLKGEN_HFO_XTAL_REG (address 0004h)
Bit Symbol Access Value Description
31:24 RESERVED R/W 0x00 Reserved
23:12 XTAL_ACTIVATION_TIMEOUT R/W 0xFFF Set the XTAL activation timeout value (in LFO Clock
8); Default value > 10 ms
11 XTAL_DETECT_ENABLE R/W 0x00 Enables the XTAL output clock presence detection if
clk_in_detect_enable is low.
1: Enable XTAL clk detection
0: Disable XTAL clk detection
10 XTAL_SPARE3 R/W 0x00 controls XTAL Spare3
9 XTAL_SPARE2 R/W 0x00 controls XTAL Spare2
8 XTAL_SPARE1 R/W 0x00 controls XTAL Spare1
7 XTAL_SPARE0 R/W 0x00 controls XTAL Pull Down
1: enable strong pull-down on clk_xtal port of clkgen_ana
sub-block
0: disable pull-down on clk_xtal port of clkgen_ana sub-
block