NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
264 of 345
Bit
Symbol
Access Reset
Value
Description
9
AHB_ADDR_ERROR_CLR_
STATUS
W
0
1 - clear AHB address overflow Error
interrupt
0 – no effect
8
AHB_ERROR_CLR_STATUS W
0
1 - clear AHB Slave Error interrupt
0 – no effect
7:3
RESERVED
W
0
Reserved
2
WATERLEVEL_REACHED_
CLR_STATUS
W
0
1 - clear water level reached interrupt
0 – no effect
1
EOT_CLR_STATUS
W
0
1 - clear EOT interrupt
0 – no effect
0
EOR_CLR_STATUS
W
0
1 - clear EOR interrupt
0 – no effect
14.2.9.16 SPIM_INT_SET_STATUS_REG
This register is a collection of Set Interrupt Status commands. Writing 1 to this register
does set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has
no effect.
Table 310. SPIM_INT_SET_STATUS_REG (address offset 0x3FEC)
Bit
Symbol
Access Reset
Value
Description
31:10
RESERVED
W
0
Reserved
9
AHB_ADDR_ERROR_SET_
STATUS
W
0
1 - set AHB address overflow Error
interrupt
0 – no effect
8
AHB_ERROR_SET_STATUS W
0
1 - set AHB Slave Error interrupt
0 – no effect
7:3
RESERVED
W
0
Reserved
2
WATERLEVEL_REACHED_S
ET_STATUS
W
0
1 - set water level reached interrupt
0 – no effect
1
EOT_SET_STATUS
W
0
1 - set EOT interrupt
0 – no effect
0
EOR_SET_STATUS
W
0
1 - set EOR interrupt
0 – no effect
