UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
128 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
18.18 User security bytes
This device has three security bits associated with each of its eight sectors, as shown in
4
WDSE
Watchdog Safety Enable bit. Refer to
Table 96 “Watchdog timer configuration”
for details.
5
BOE1
Brownout Detect Configuration (see
Section 5.1 “Brownout detection”
6
RPE
Reset pin enable. When set = 1, enables the reset function of pin P1.5. When cleared, P1.5 may be used as
an input pin. NOTE: During a power-up sequence, the RPE selection is overridden and this pin will always
functions as a reset input. After power-up the pin will function as defined by the RPE bit. Only a power-up
reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the
RPE bit.
7
WDTE
Watchdog timer reset enable. When set = 1, enables the watchdog timer reset. When cleared = 0, disables
the watchdog timer reset. The timer may still be used to generate an interrupt. Refer to
for details.
Table 112. Flash User Configuration Byte 1 (UCFG1) bit description
…continued
Bit Symbol
Description
Table 113. Oscillator type selection
FOSC[2:0] Oscillator configuration
111
External clock input on XTAL1.
100
Watchdog Oscillator, 400 kHz ± 5 %.
011
Internal RC oscillator, 7.373 MHz ± 1 %.
010
Low frequency crystal, 20 kHz to 100 kHz.
001
Medium frequency crystal or resonator, 100 kHz to 4 MHz.
000
High frequency crystal or resonator, 4 MHz to 18 MHz.
Table 114. Flash User Configuration Byte 2 (UCFG2) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CLKDBL
-
-
-
-
-
-
-
Unprogrammed
value
0
x
x
x
x
x
x
x
Table 115. Flash User Configuration Byte 2 (UCFG2) bit description
Bit Symbol
Description
0:6 -
Not used.
7
CLKDBL
Clock doubler. When set, doubles the output frequency of the internal RC oscillator.
Table 116. Sector Security Bytes (SECx) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
EDISx
SPEDISx
MOVCDISx
Unprogrammed
value
0
0
0
0
0
0
0
0
