UM10540
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
4 of 7
NXP Semiconductors
UM10540
NVT2001GM and NVT2002DP demo boards
2. Hardware
description
2.1 Schematic
The demo boards contain footprints for the NVT2001GM and NVT2002DP devices, where
the jumpers, headers, and passive components are shared. The NVT2001GM and
NVT2002DP demo board schematic is shown in
. Pins 2 and 3 on J1 must be
shorted to enable the part. Pins 4 and 1 on J3 are power and GND for the low voltage
side. Pins 4 and 1 on J4 are power and GND for the high voltage side. All Bn I/O pins on
the right side have 10 k
Ω
pull-up resistors to VREFB and all An I/O pins on the left side
have 10 k
Ω
pull-up resistors to VREFA through jumper J2. A shunt needs to be installed
at J2 if VREFB
−
VREFA < 1 V. If VREFB
−
VREFA
≥
1 V, then J2 should be open and
resistors R2 and R3 must be removed. If they are not removed, then a resistive path
exists between the A-side I/Os that can impact the efficiency and signal integrity of the
solution.
Fig 2.
NVT2001GM and NVT2002DP demo board schematic
002aag940
EN
VREFB
B1
B2
8
7
6
5
VREFA
A1
A2
2
3
4
GND
1
NVT2002DP
R3
10 kΩ
R2
10 kΩ
U1
A2
GND
2
1
A1
3
VREFA
4
low voltage
A-side
header 1
×
4
J3
21
J2
JP
Jumper:
ON: if VREFB − VREFA < 1 V
(populated 10 kΩ pull-up resistors)
OFF: if VREFB − VREFA ≥ 1 V
(do not populate 10 kΩ pull-up resistors)
EN_Vb
R1
200 kΩ
C1
0.1 μF
R5
10 kΩ
R4
10 kΩ
B2
GND
2
1
B1
3
VREFB
4
J4
high voltage
B-side
2
3
1
J1
2-3: switch enable
1-2: switch disable
EN
VREFB
B1
6
5
4
VREFA
A1
2
3
GND
1
NVT2001GL
U2
EN_Vb
header 1
×
4
